PLL outputs to drive 50 ohm loads

[Altera_Forum]

I need two outputs from a single PLL of CYCLONE-III 3C16. Both the outputs are single-ended. One of outputs is 100MHz and the other is 120MHz-200MHz which will be dynamically configured through NIOS-II with variable phases. Those two outputs should be phase-synchronized. They are going to drive two separate loads of 50 ohm for impedance matching. I wonder if the PLL can provide up-to 30mA for each output in order to drive those two loads of 50 ohm . If not, please recommand practical solutions. Many thanks.

[Altera_Forum]

The maximum ratings say -25/+40 mA, also internal series termination isn't supported for the 3.3 V node. It mainly depends on the required receive level which isn't nebtioned in your post.

[Altera_Forum]

If you are driving a single load from each output consider using serial termination as it avoids the constant DC load of the parallel termination at the far side. In Cyclone III (and most other devices) series termination is easy.

[Altera_Forum]

Thanks. I did consider using series termination. However, it is not as good as parallel termination. If Cyclone III series termination is used, 2 extra I/Os, rup and rdn will be used or 2 external resistors will be used.

[Altera_Forum]

--- Quote Start ---  However, it is not as good as parallel termination.  --- Quote End ---  In which regard? For LVTTL/LVCMOS outputs, parallel termination can't be used. Calibration resistors rup and rdn would be needed with calibrated termination only.

[Altera_Forum]

Thanks. 

 One of clocks goes to a high-speed DAC in single-ended mode. In the single-ended mode, it needs 50ohm parallel termination for its best performance. The DAC could accept LVDS. The issue with LVDS from Cyclone-III FPGA is that a bank has to be configured as LVDS. As a result, we don't have enough I/O pins.    The other clock (120MHz-200MHz) goes to the single-ended clock input of a device. Ideally, it is in 50ohm parallel termination.    I can find up-to 166MHz clock drivers which are able to drive single-ended 50 ohm impedance with 2 inputs being synchronized.

[Altera_Forum]

You can (almost) always use serial termination for single-ended point to point connections. I overlooked FvM's observation that unfortunately you can not apply series terminations for 3.3V outputs. I suggest you add a series resistor externally. The trick here is to estimate what the series resistance of the driver inside the FPGA is, I usually specify a 39 ohm external resistor for a 50 ohm Z0. A 0402 resistor can fit directly to the BGA escape via. Also the transmission line you route on the PCB doesn't have to be a 50 ohm either, you could opt to route for 60 ohm (or even more).

[Altera_Forum]

For best DAC (or ADC) performance, you shouldn't use a clock from a FPGA PLL. The clock jitter introduces a considerable phase noise amount. This is particularly the case in communication (or similar measurement) applications, where a high frequency signal is generated by the DAC. A LVDS output high frequency crystal oscillator will give better performance for this application.

[Altera_Forum]

I understand what you were saying. In my case, I have to use a PLL clock output to drive the DAC clock input. This is because the DAC clock and DAC digital data lines from the FPGA are not independent. The DAC clock has to be synchronized with the other clock.

[Altera_Forum]

I mainly stumbled upon best performance. You can expect good performance with FPGA PLL clock, I'm using it in many projects. But if you check the PLL jitter specification, it really isn't outstanding. As an additional problem, using single ended IO standard, you also add FPGA originated switching noise and respective jitter to the clock output. A differential standard would be better, the same applies to the FPGA master clock input.

[Altera_Forum]

Correct me if I'm wrong but it appears based on the current calculation that bcao is using a 1.5V single-ended standard correct?  

 Why not use a termination similar to SSTL Class I or HSTL Class I. Reference page 6-14 of the following document: http://www.altera.com/literature/hb/cyc3/cyc3_ciii5v1_02.pdf  Jake

[Altera_Forum]

The VCCIO hasn't been mentioned. For some reason I expected 3.3V, but this is possibly wrong. However, there is effectively no difference in output driver operation between SSTL and other single ended standards. Both are choosing a driver impedance by enabling or disabling output transistors (from three or four available). Depending on the IO standard, it's either named drive strength or series termination.

[Altera_Forum]

FvM and jakobjones, thank you very much. The receivers in my application do NOT accept Vref and this is one of reasons SSTL Class I or HSTL Class I was not considered. At 3.3V level, as FvM said, FPGA is not able to source or sink enough current to a 50 ohm parallel termination. I am going to use 2 separate clock drivers to drive 2 50-ohm loads although there will be some differences of jitters and delays. The solution is to use a configurable PLL and dynamically adjust phase shift through NIOS-II.