Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Timing reports

Altera_Forum
Honored Contributor II
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I have problems to confirm my timing with Timequest Analyzer. I just constraint my base clock and try now to find out , the setup time and hold time from sdram_data in relation to the clk_sdram. 

I always get the message: “Info: Report Timing: No setup paths were found” 

Do I have to constrain my design first before I can ask for reports?
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Altera_Forum
Honored Contributor II
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Everything in TimeQuest is constraint based. If you've constrained your clocks, then the internal timing is constrained, but you'll need to add set_input_delay and set_output_delay constraints to your I/O ports so they can be properly analyzed. 

 

(You can use the report_path constraint, which analyzes paths without a constraint, which will work for now, but I recommend constraining everything so the reports are already done for you and so the fitter works to meet your constraints.)
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Altera_Forum
Honored Contributor II
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Thanks for your answer!

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