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i'm using cyclone 3 and maxII devices. in the two devices i have a 10Hz clock that i need them to be synchronized.
i don't have avaliable pins to use, so i thought using the INIT_DONE or CONF_DONE as an enable to the CPLD 10 HZ clock. i'm not sure if it is possible, and i wanted to know what is the delay between those signals to the real time in which the FPGA will start his 10HZ clk.Link Copied
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This is a really bad idea. both clocks will drift in time, so even if it works for a couple of secods, there is no guaranty that it will work for hours.
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