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SystemVerilog in SOPC Builder

Altera_Forum
Honored Contributor II
‎06-09-2008 07:24 AM
927 Views

I am trying to add a component that's written in systemverilog to sopc builder 8.0. Quartus compiles and runs this code on the hardware just fine, but sopc refuses to even use the file. It seems to be calling the compiler with the wrong settings. Anyone know how to fix it?

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Altera_Forum
Honored Contributor II
‎06-09-2008 07:35 AM
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ok, I figured it out. You have to add the following synthesis directive at the top of the file: 

 

// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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