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Hi, I am trying to make a counter which counts until timeout. Quartus II doesn't support using "wait for" or "after"? Then what can I do to end the process after a while?:confused:
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_test is
port (
CLOCK_50MHz: in std_logic;
fin: out bit;
);
end entity counter_test;
architecture behav of counter_test is
signal fin: bit := '0';
begin
process (CLOCK_50MHz)
-- variable sub_cnt : integer := 0;
constant timeout:time:=10 ms;
begin
if (CLOCK_50MHz'event and CLOCK_50MHz = '1')then
cnt <= '1' after timeout;
-- sub_cnt := sub_cnt + 1;
end if;
-- wait until (CLOCK_50MHz'event and CLOCK_50MHz = '1') for timeout;
end process;
end architecture behav;
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I am trying to make a synthesizable code. I made some mistakes in the previous code, now I changed it but it still doesn't work. I can compile it but the reault after simulation is not what I'm expecting. I am totally confused about how to impelement a time limitration here. I am using QuartusII, and that software doesn't support "wait for"......
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--- Quote Start --- I am trying to make a synthesizable code. I made some mistakes in the previous code, now I changed it but it still doesn't work. I can compile it but the reault after simulation is not what I'm expecting. I am totally confused about how to impelement a time limitration here. I am using QuartusII, and that software doesn't support "wait for"...... --- Quote End --- Hi, I suggest you to have a look at quartus vhdl templates (there are counter examples I think) and a get a good book (or tutorials or good examples) about synthesizable VHDL code. http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style "wait until" "after" are ignored by Quartus synthesizer. Have a nice day.
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