How does Quartus handle flip flop with both async reset and set

[Altera_Forum]

I have come to know that Stratix iii and Iv do not support async set ,so how in Quartus handles simulatanoous reset and set (async) ,I have heard that it uses latch but don't know exactly,Plz do clarify... 

Here is the verilog code for a DFF with async set and reset  module DFFASR(Clk,D,Q,Qbar,Set,Reset); input D,Clk; input Reset,Set; output reg Q; output Qbar;  assign Qbar =~Q;  always @(posedge Clk or posedge Set or posedge Reset) begin if(Set)  Q <= 1'b1; else if (Reset)  Q <= 1'b0;  else  Q<= D; end  endmodule

[Altera_Forum]

For your curiosity - 

 It will build a register with XORs on the D and Q side, controlled by a latch. The easiest way to think of it is that the latch controls whether the register is active high or active low. Presetting will clear and make the register active low. Clearing will clear and make the register active high. Multiple registers with the same secondarys can share one latch.  For your coding style / sanity -  Don't do that.

[Altera_Forum]

have you heard of a techinique called 3 flip flop transformation method when both async set and sync reset is used??? 

I have heard from few people but don't know in detail...

[Altera_Forum]

You could use 2 FF's to screen instead of the latch (for a total of 3) - 

 always @(posedge clk or posedge aclr) if (aclr) aclr_ff <= 1'b0; else aclr_ff <= 1'b1; always @(posedge clk or posedge apre) if (apre) apre_ff <= 1'b0; else apre_ff <= 1'b1; always @(posedge clk) d_ff <= din; assign q = aclr_ff & (!apre_ff | d_ff);  This isn't exactly equivalent if you clear, then preset before the next clock tick. It also has more timing critical signals to route than the latch version.

[Altera_Forum]

Can you mail me a circuit diagram of the latch tranformation ,I didn't get the exact logic.... i can try understanding using the circuit diagram. 

My mail id is ashish.tronics@gmail.com

[Altera_Forum]

Hello, 

 I'm surprised at it. I know this flip flop can't be implemented to cyclone series, but can be to stratix ii. I thought the stratix iii has basically same architecture as the stratix ii, but actually it isn't.

[Altera_Forum]

The actual registers in these devices support asynchronous clear. To support asynchronous preset rather than clear, they do what's called NOT gate push back, which I never found to be the most obvious description of the process. Basically, they just invert the register's input and output, effectively changing the power-up state from GND to VCC. Now when you clear the register, it will behave like a preset.  

 If you want both clear and preset, then you need another asynchronous control signal. In the older families before Stratix III, you could use an aload. I guess this feature wasn't worth the bang for the buck, so to speak, because it was removed. The latch emulates it more or less satisfactorily but better to remove the requirement from a design entirely.

[Altera_Forum]

Hi all,  

I am implementing a FPGA prototype of an ASIC on Stratix-III FPGA.   I am having also async CLR and SET in my RTL (ASIC RTL). To keep the functionality I have to perform as less as possible RTL modifications on the ASIC RTL. I noticed that such stucture leads to combinational loops in the synthesis and long P&R compile time. I also suspect that many gated clocks are not converted due to such warnings.   Do you have any idea how to modify the RTL to keep the functionality as the ASIC RTL and prevent combinational loops?   Regards

[Altera_Forum]

If you need asynchronous set and reset, there's no alternative to the combinational loop and xor solution used by Quartus, I think. I don't see a problem with the combinational loop as such, but the synchronous datapath is considerably slowed down by the additional LUTs. The additional resource and routing effort may be an issue with a large amount of set/reset FFs in your design.