Use Stratix II PLL to generate clock with deviations and jitter?

[Altera_Forum]

Hi,  

 after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g. 25 MHz) and continously dynamically reconfigure the phase, for several purposes:  

1. Make the clock slightly slower or faster (say, 200 ppm) 
2. Introduce more or less random jitter 
3. Introduce additional phase modulation 

  That would be very convenient for several tests that we're planning with a prototype setup. What is your opinion? Can this be done? Maybe it is readily available for purchase or even as a free reference design?  Thanks for your comments in advance! Kolja  -- http://www.ixo.de (http://www.ixo.de)

[Altera_Forum]

Kolja: 

 I think your first purpose (slightly changing the freq.) is possible. Also, if you can't get the resolution you want using one PLL, maybe you can daisy-chain two--which is kind of an ugly solution, but possible. As far as introducing jitter, I'm not sure how accurately you want to model jitter, but I think it will be really tough to do. Are you planning on changing the duty cycle randomly as fast as you can? What did you have in mind? For the third purpose (phase mod.) you can probably do a rough emulation of this. If you can limit yourself to changing the parameters of the PLL that do not require you to re-sync you might be able to do this.  -B

[Altera_Forum]

Hi, thanks for your reply.  

 > What did you have in mind?  Generally, the plan is to build a prototype for a data transmission system (somewhat similar to Ethernet 100FX: 125 MBps transmitted with NRZI encoding).   The prototypes are based on a ready-made board with Stratix II (the DBF2S30 from devboards.de). Not that we really need a Stratix, but because it features a fine modular concept and can carry up to 7 extension modules, which perfectly fit our requirements. A single board can simulate our whole system.  Now that we have the Stratix anyway and some unused PLLs in it, I thought it would be convenient to be able to use it as a source for stress tests... to prove that our transmission system can be pushed to the limits as per specification.  Kolja

[Altera_Forum]

BGG is right - for the first purpose, pll reconfiguration will work. For the other two it will not. You cannot change the phase or duty cycle quickly enough to allow you to emulate deterministic jitter.

[Altera_Forum]

Okay, the phase reconfiguration works fine. I'm able to "pull" a 25 MHz clock slightly up or down, max 1300 ppm. That's better than any VCXO that I could use. 

 For (some kind of) jitter I now consider to switch between several clocks (derived from the same base with different phase offset). The switching would have to occur in the exact middle between transistions.   We'll see if that works...  BTW, Is there some "standard" way to implement some kind of delay line without doing manual placement/routing?   Thanks for your answers Kolja

[Altera_Forum]

Unfortunately, no. Implementing delay lines in FPGAs is not highly recommended because of the fluctuations you can see based on placement, process, voltage and temperature. If you must do this, you will need to manually place the delays to eliminate at least one of the four variables. The others, especially process, are beyond your control.