Counter Power on Reset only

[Altera_Forum]

Is there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise. 

 (I am using EP2C35F672C6 "Cyclone II" within DE2 board)

[Altera_Forum]

what do you actually mean? Please give some more details.

[Altera_Forum]

Registers have a power on reset state, it can be defined e.g. as an initial value in VHDL signal definition.

[Altera_Forum]

--- Quote Start ---  what do you actually mean? Please give some more details.  --- Quote End ---    A sample code will make me easier to explain:  module myTest(clk,_reset,outcnt);  input clk,_reset;  output reg [7:0] outcnt;    always @(posedge clk or negedge _reset)  begin  if(_reset==1'b0) outcnt<=8'h00;  else outcnt<=out+1'b1;  end endmodule  Here, _reset is connected to external switch. So, anytime someone pushes that switch, outcnt becomes 8'h00.   But, what I really want to happen is that I want outcnt be zero only at Power ON.  (If I remove _reset signal, what will the initial value of the outcnt at Power ON?) Is there anyway I can work on DE2 board with Altera 2c35 or Quartus S/W to specify this?  Thanks.

[Altera_Forum]

I'm not so familiar with Verilog, but Quartus should infer register power-up reset from Verilog initial block: 

initial begin outcnt<=8'h00; end There is also an power-up option for registers in assigment editor, but HDL assignment is more comfortable.

[Altera_Forum]

The register will have the power up condition as stated in the verilog design.  

 I found some instructions on how it can be done different in the quartus help :   // Use a variable declaration assignment to set the power-up level // of an inferred register. reg q = 1'b1; always@(posedge clk) begin q <= d; end  So it was time to do some tests :   - when a reset condition is specified in the verilog code like this :    reg q; always@(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end  Then the reset condition (q <= 0 ) is used as startup value, regardless the specified initial condition. Even if I set "reg q = 1", the value for the register is zero after configuration.  - when you don't specify a reset condition in the always block, the initial condition specified is used.  However I didn't found a way to visualize the reset condition in the quartus environment (also not in the chip editor).   Stefaan

[Altera_Forum]

I think, a power-up condition different from asynchronous reset doesn't make much sense. However, from hardware description, I expect that both options exist independantly. In some cases, the power-up level is ignored during synthesis, but you get a warning then. 

 It could be that the asynchronous reset input is triggered unintenionally at power-up. You can use an asynchronous input gated somehow with another signal to see, if the power-up level is still ignored.  According to Verilog IEEE standard, the variable declaration assignment you used should be equivalent to assignment in an initial block.

[Altera_Forum]

You are right if you say it makes no sense to have a different behaviour.  

I think most fpga's does not get 'reset' in the sense that you electrically pull a pin up or down. The 'reset' is just part of the configuration process.  This way the synthesis of my little example follows the correct path : no difference, and the reset condition is used if any is specified. If howerver, no reset condition is given, you can specify it in an other way, using the initial condition.   Stefaan

[Altera_Forum]

There is another aspect of power-up level that should be noticed. Quartus II software manual explains how power-up level is achieved: 

  --- Quote Start ---  Registers in the device core always power up to a low (0) logic level on all Altera devices. However, there are ways to implement logic such that registers behave as if they were powering up to a high (1) logic level.  --- Quote End ---   Depending on the device family, some combinations of asynchronous set/reset and power-up level may be excluded. In this case you get a serious warning, as I mentioned. Also, the (1) power-up level may consume additional logic resources.  To my opinion, it's generally useful, to have a hardware reset with FPGA. I sometimes missed it, when it was omitted. An unrelated asynchronous reset may cause undefined behaviour when it is released simultaneously with active clock edge, so it should be better released synchronously. It's easy to combine this circuit with a register or a delay counter that generates a power-on reset also when the hardware reset is missing.

[Altera_Forum]

--- Quote Start ---  I think, a power-up condition different from asynchronous reset doesn't make much sense. However, from hardware description, I expect that both options exist independantly.  --- Quote End ---    It depends on the device. In this case, Cyclone II, I know from experience that it is not possible. Power-up level must be the same as the async reset one. Quartus definitely issues a warning (or an error, I don't remember for sure) when the power-up and async reset levels are incompatible.

[Altera_Forum]

It's a "severe warning" that power-up level is ignored. Actually the statement you quoted from my previous post was incorrect, cause power-up level isn't a hardware feature but an option created by the synthesis tool utilizing the fixed low power-up level. For FPGA families not having asynchronous set and reset, the settings may be incompatible as you reported.

[Altera_Forum]

Cyclone II physical registers always power up to 0, and have ACLR support. When the designer requests either APRE or power up to 1 the software will emulate it with not-gate-push. To not-gate-push inverters are added before and after the register, and the APRE changes to an ACLR. This makes the register look like it powers up to 1 as viewed from surrounding logic. Mismatching power / reset states can be emulated with some extra logic, or implemented directly on some of the other chip families, but it's pretty unusual. 

 Quartus will recognize the "initial" described by FvM above. If there is no initial assignment to 1 or 0 the rule is actually "don't care" by default. It will show power up to "X" in modelsim, and Quartus may select a 1 if it can use the 1 to reduce the logic. Otherwise it sticks to the natural 0.