DDR2 Design with Cyclon III

[Altera_Forum]

Hi all 

 I just started a new desing using a Cyclon III to interface discrete DDR2 memory (No DDR2 module!). It is just one single chip per interface.   Can someone help me choosing the right on board termination?  From other threads and Altera App Notes I know there is ODT on data lines and a few others, but not on address lines. I notice that all DIMM Moduls have 22R series resistor mounted.  I would like to use as few resistor as possible to simplify routing and reduce board coast. DDR2 clock freq. is 167MHz at max.   My approach would be: - Do nothing on all lines that features ODT in DDR2 (so I rely on ODT and OCT of the cyclon III) - Do nothing on clock and other lines, as well. I could use Cyclon III OCT for series resistor if necessary  - I should be able to route everything with short pcb traces, as the FPGA pin usage is low to medium  What is your opinion? Could this work or do I need some termination?  Is there some kind of design example or reference design?  Thanks for any hint  Alex

[Altera_Forum]

Some thoughts, 

 At 167 it is relatively slow and relatively fast (sounds odd, I know).  You might be able to get away with nothing (maybe just the clock?).  Best bet is to get yourself an evaluation version of Mentor's Hyperlinx and build up a model of the desired interface you wish to use.  Then you will be able to experiment with different options. (You could even ask the Mentor FAE to work it up for you as the demo he will show you for the tool). Avatar

[Altera_Forum]

its not the speed of the bus that causes your problems, its the speed of the edges. 

 it is possible to select series termination on the address & ctrl lines as well as the data lines. just open up the assignments editor and add them manually.   select "output termination" for "assignment name", and then select whichever OP impedance you desire... I recommend 25R.  Have you tried any of the Altera Megafunctions?  You should do as Avatar suggested and simulate using Hyperlynx. better to be safe than sorry. all IBIS models can be downloaded from the Altera web site.  Hope this helps

[Altera_Forum]

Hello Kleckse, 

 I suggest you have a look on this webpage: http://www.rickmiller.com/si.htm (http://www.rickmiller.com/si.htm)  As RedSavina previously said, the key thing is not the clock speed but the edge speed of your signal. Nowadays, FPGA are better than 10 years ago, thus the gate commutations are very fast. If a trace is too long between 2 components you can have some reflexion due to the track impedance and you can experiment some bad waveform signals (wrong detection and so)... Refer to Maxwell formulas... ;-)  I'm currently designing a custom Cyclone III board with SDRAM, SRAM and Flash and I had to think on this problem. My clock is at 50Mhz and SDRAM is 100Mhz, I chose to place components very close and try to minimyse the distance between all memory chips and FPGA (< 2.5cm).  Here is my approach to choose termination resistor:  1) Know your maximum signal edge speeds and try to design your PCB by minimysing all the track distances. You should find some "rules of thumb" in the attached webpage to calculate the maximum track distance depending of the edge speed. If you can design a track smaller than the maximum distance you should not need a termination resistor.  2) If you can't reduce the track, you will probably have some signal reflexion on the track. The idea is the emitter driver should generate a waveform signal with a smaller amplitude (divided by 2) in order to retrieve a "normal" amplitude waveform at the receiver side. To do that you need to add a resistor just close to the emitter output to get a voltage divider with the track impedance. For instance: If Z_track = 25 ohms choose R_term = 25 ohms.  By applicating this rule it means when you have a bidirectionnal signal you should put a R_term at the output of each emitter driver (1 resistor ---- track ----- 1 resistor). In this case you can put only 1 resistor at the middle of the track.  Summaryze:  - mono-directionnal signal: 1 resistor close to the emitter driver - bidir-signal: 1 resistor at the middle of the track  3) Nowadays, Cadence and Mentor have specific tools to compute automatically for each track if it needs a terminator resistor, the value and the position...  I hope it will help you.  Regards, -Pierre

[Altera_Forum]

Did you have any lack??? How does DDRAM II works with Cyclone III works for you now??

[Altera_Forum]

Hi 

 I am still developing the board. Now I am just before starting to layout the PCB.  I have done a lot of simulating for signal integrity. I simulated for 167MHz Clock speed. All traces impedanz controlled to approx. 50Ohm  This is what i found out: - If i keep the lines below 3cm in length I don't need any termination due to reflexions - Need to control drive strength in FPGA to eliminate over/undershoot - Need to run DDR2 in reduced drive strength - clock termination 100Ohm diff.   Bottom line is: Except for clock there is no additional termination on board, but we need to reduce drive strength.  Alex

[Altera_Forum]

INteresting... I did the same and ended up putting series termination resistors and pull ups on address lines and control lines, I am using 200MHZ clock, trace less then 2", 3C16 Cyclone device and MT47H32M16 from Micron DDRAM II. Can you tell what rising/filing time you getting from your simulation??

[Altera_Forum]

Rise time is approx 660ps, fall time is approx. 840ps. clock edge is clean and monotone. 

 I use MT47H64M16 from Micron and Simulation models for EP3C120 even if we will acctually mount an EP3C40 or 55

[Altera_Forum]

Alex, 

  I think it is to long 660/840 pS I have around 230-240pS. How far are you with development? I am in layout now.  Also are you planning to use Altera DDRAM core or planning to develop something in your own??   Also if you want PM me, where are geographically ?  Regards,     Iouri