SOPC - simple question

[Altera_Forum]

Hi, 

 I am new here, so sorry for trivial questions:-)  It's my first project in SOPC Builder (I use 5.1) and I'd like to add something very simple in order to learn how to use the tool.   My VHDL code is simple counter from Altera site. But when I try to use Component editor, I see error: "slave must have a read or write interface, or support interrupts." I cannot add result signal. In signals tab there is only clock signal, which I set to type clk.  I read tutorials, I finieshed it step by step but there was nothing about it.  Here is code: LIBRARY ieee; USE ieee.std_logic_1164.ALL;  ENTITY count IS  PORT  (  clock: IN STD_LOGIC;  result: OUT integer RANGE 0 TO 31  ); END count;  ARCHITECTURE rtl OF count IS  SIGNAL result_reg : integer RANGE 0 TO 31; BEGIN  PROCESS (clock)  BEGIN  IF (clock'event AND clock = '1') THEN  result_reg <= result_reg + 1;  END IF;  END PROCESS;  result <= result_reg; END rtl;   Thank you for any help!  Best regards, Koza

[Altera_Forum]

I am new too, but I hope that my short experience can be useful for you. A component in SOPC builder is a module that talks with Nios core and with external modules or directly with the exterior of the FPGA. For this reason, It´s necessary that the new componet that you created has any relationship with the nios and a counter hasn´t it. Maybe you have to choose other example like a memory interface or rs-232, you can find it in www.opencore.org. 

 Best regards

[Altera_Forum]

Thank you for your reply, I tried adding this counter, because I'll need it soon. I use uClinux and I'd like to read counter value from NIOS2 memory to see how many cycles some part of the code takes. 

  With best regards, Michal

[Altera_Forum]

--- Quote Start ---  It's my first project in SOPC Builder (I use 5.1).  --- Quote End ---     Use version 7.1. There have been major changes in SOPC Builder. Especially if you are just now learning the tool, learn the current version.

[Altera_Forum]

The SOPC builder is integrating peripherals onto the Avalon switch fabric so the processor (typically a NIOSII) can access them. So any HDL imported using the component editor needs to have a minimal set of Avalon signals. Components can be imported as masters, slaves, or nios custom instructions (hardware that goes into the CPU instead of onto the bus). They can be mapped as register or memory, which determines how byte lanes are handled (ie dynamic bus sizing or fixed byte lanes). ** 

 For instance, to read a 32-bit counter you would need (clock, chip select, 32-bit data, read enable). This requires some modification to your VHDL.  An alternative approach is to add a PIO (parallel i/o port) to your SOPC Builder system set up to be a read-only port. Name the PIO something like "counter_port"; you will then see pins with this name added to the generated design. In the schematic or HDL where you instantiate the NIOSII/SOPC component connect those pins to your counter. When the processor reads the PIO it will be reading your counter. This requires no modification to your counter.  ** (Version 7.1 adds an additional streaming type of peripheral and designates the traditional peripheral as "memory mapped".)

[Altera_Forum]

Thank you for your response! 

 I implemented my counter using PIO and it seems to work!   But now, I want to add an option to clear my counter and here I have a question: may I simply connect PIO output port to PIO input port of my counter? I did it but something is wrong, it doesn't want to change value to zero... I am not sure which address should be changed: base, end or the whole page?  Thanks in advance for your help, Best regards, Koza  PS. Part of my design file showing (I hope) the problem can be found here: www.twojekorki.republika.pl/clear.jpg PS2. If someone plays with uclinux, my code was something like that: # define READ_C (*(unsigned int *)0x10) # define ZERO_ADD (*(unsigned int *)0x20)  //clear ZERO_ADD = x0ffffffff; ZERO_ADD = 0; //read int r = (unsigned int)READ_C;

[Altera_Forum]

Add another PIO set up to be an output and use it to control the counter clear line.

[Altera_Forum]

Everything is fine now, thank you! 

 Regards, Koza

[Altera_Forum]

Noo, not again, there is still something wrong. I did like you said - connected output PIO from NIOS to clear input of my counter but it doesn't want to change value to 0!  

Below is my code: LIBRARY ieee; USE ieee.std_logic_1164.ALL;  ENTITY count IS  PORT  (  set_zero: IN STD_LOGIC;  clock: IN STD_LOGIC;  result: OUT integer  ); END count;  ARCHITECTURE rtl OF count IS  SIGNAL result_reg : integer; BEGIN  PROCESS (clock)  BEGIN   IF (clock'event AND clock = '1') THEN  IF (set_zero = '1') THEN  result_reg <= 0;  ELSE  result_reg <= result_reg + 1;  END IF;  END IF;  END PROCESS;  result <= result_reg; END rtl;   and at the url I mentioned before there is part of my bsf shown.   Please, help:-)  Regards, Koza

[Altera_Forum]

FYI there is a component in SOPC Builder called the "Performance Counter". It comes with a Nios II driver and can monitor multiple sections of code.

[Altera_Forum]

Thanks for your help, finally I added volatile keyword and I disabled cachce and it works now. 

  Best regards, Koza

[Altera_Forum]

Ok, then your accesses to the peripheral were being cached. To avoid this with a processor with data cache use this: 

 # include "io.h" // contains cache bypassing macros   IORD (base, offset); // base address and word address in the peripheral IOWR (base, offset, data); // base address, word address, and the data you want to write  Those are for accessing native (registered) components like the one you created. If you need to bypass cache to access memory (dynamic) components there are similar macros in io.h for those only they use byte addressing instead of word addressing. They should be contained in this document:  http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf  Also the keyword volatile tells the compiler to not optimize away code. For example if you read from a memory location polling for a specific value, you should make it volatile otherwise the compiler may get rid of the polling loop. The compiler would do this since it would see the multiple accesses to the same location and remove it since it doesn't know that some external event might change that value. So it would remove the loop and only read it once (thinking the value will never change so the loop isn't necessary).