Anyone know about ERIKA Enterprise RTOS?

[Altera_Forum]

I am recently working on a multiprocessor project. 

and find ERIKA Enterprise does the same thing. It helps to build a multiprocessor project,  I don't know whether it is supportive for uclinux system on NIOSII?

[Altera_Forum]

The NIOS uCLinux does not support SMP (Symmetrical Multi Processor i.e. multiple processors are managed by the OS).  

 But you can define multiple processors in the FPGA and have one of them run uCLinux, while the other(s) do dedicated realtime work, e.g. in a "closed loop" application.   I suppose in most applications this makes more sense, anyway.   -Michael

[Altera_Forum]

<div class='quotetop'>QUOTE (mschnell @ Jul 24 2009, 09:42 AM) <{post_snapback}> (index.php?act=findpost&pid=23273)</div> 

--- Quote Start ---  The NIOS uCLinux does not support SMP (Symmetrical Multi Processor i.e. multiple processors are managed by the OS).   But you can define multiple processors in the FPGA and have one of them run uCLinux, while the other(s) do dedicated realtime work, e.g. in a "closed loop" application.   I suppose in most applications this makes more sense, anyway.   -Michael[/b]  --- Quote End ---   Thank you for you reply!! Yep,my suppose for the project frame is like you said. My original purpose of this thread is to ask whether ERIKA Enterprise will help, in the frame just like you said. It seems like you have done the multiple processor case, can you give more details about the &#39;closed loop&#39;? Take an example of 2cpu. cpu0 charges with uclinux, cpu1 charges with realtime work. what storage space (sdram,on-chip..)should each one use? imagine the cpu0 startup firstly,how to trigger the cpu1 run with"closed loop"? looking forward to your reply,thank you very much!!

[Altera_Forum]

In fact I did not do any multiprocessor stuff, myself, but here in the forum we already had several discussions on this issue, that, unfortunately, are lost now due to the disk crash. AFAIK, there have been several successful projects done in this way.  

 With "closed loop" I mean using the processor without a formal OS, just run it in a permanent loop and have it do the stuff it needs to do whenever necessary either as a part of the loop or in an interrupt service routine.  The most interesting part is the communication between the processors. You can e.g. do FIFOs in hardware or use shared memory protected with a hardware MUTEX (Altera does provide such a Mutex in the Avalon Bus). Of course you can just use a pair of (Fifoed)Uart and connect RxD and TxD.  -Michael

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  it needs to do whenever necessary either as a part of the loop or in an interrupt service routine.[/b]  --- Quote End ---   I am not so clearly understand "a part of the loop" and "an interrupt service routine", since you have witnessed many successful cases in the forum, can you provide me with much more detailed clues? I have browsed many websites and got little information.  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  The most interesting part is the communication between the processors. You can e.g. do FIFOs in hardware or use shared memory protected with a hardware MUTEX (Altera does provide such a Mutex in the Avalon Bus). Of course you can just use a pair of (Fifoed)Uart and connect RxD and TxD.[/b]  --- Quote End ---   I have viewed shared memory one in much of the material I gathered. But it is the first heard of the FIFO one. Are RxD and TxD the real names of the module?  Looking forward to your reply,thank you very much!! :rolleyes:

[Altera_Forum]

Replace "closed loop program" simply by "small program without an OS. This is what I mean.  

 By FIFO I mean a hardware device that transfers data from one end to the other and can store some words to synchronize vatying input and output speed  RxD and TxD are the send and receive signals of an UART(-iPcore).  -Michael

[Altera_Forum]

<div class='quotetop'>QUOTE (mschnell @ Jul 25 2009, 01:02 PM) <{post_snapback}> (index.php?act=findpost&pid=23280)</div> 

--- Quote Start ---  Replace "closed loop program" simply by "small program without an OS. This is what I mean.   By FIFO I mean a hardware device that transfers data from one end to the other and can store some words to synchronize vatying input and output speed  RxD and TxD are the send and receive signals of an UART(-iPcore).  -Michael[/b]  --- Quote End ---    Thank you sooo much!! VERY clear explaination. If I replace the FIFO with mailbox as the use of a share memory. Would it be easier? I just read some materials about mailbox core. 

[Altera_Forum]

<div class='quotetop'>QUOTE (babysnow @ Jul 27 2009, 03:33 PM) <{post_snapback}> (index.php?act=findpost&pid=23281)</div> 

--- Quote Start ---  If I replace the FIFO with mailbox as the use of a share memory. Would it be easier? I just read some materials about mailbox core.[/b]  --- Quote End ---   Not really. A FiFo separates the to processors completely like a data cable. No need for additional synchronization very simple programming logic. Shared memory needs a semaphore (Mutex) to protect mutual accesses (e.g.for delivering and accepting messages, see appropriate literature). Altera does provide such a hardware Mutex fr the Avalon bus. You need to do appropriate software to work decently with same.   -Michael 

[Altera_Forum]

<div class='quotetop'>QUOTE (mschnell @ Jul 27 2009, 04:36 PM) <{post_snapback}> (index.php?act=findpost&pid=23289)</div> 

--- Quote Start ---  <div class='quotetop'>QUOTE (babysnow @ Jul 27 2009, 03:33 PM) <{post_snapback}> (index.php?act=findpost&pid=23281)  --- Quote End ---    --- Quote Start ---  If I replace the FIFO with mailbox as the use of a share memory. Would it be easier? I just read some materials about mailbox core.[/b]  --- Quote End ---   Not really. A FiFo separates the to processors completely like a data cable. No need for additional synchronization very simple programming logic. Shared memory needs a semaphore (Mutex) to protect mutual accesses (e.g.for delivering and accepting messages, see appropriate literature). Altera does provide such a hardware Mutex fr the Avalon bus. You need to do appropriate software to work decently with same.   -Michael [/b]  --- Quote End ---    Thank you for your reply. The Mailbox Core datasheet says that it owns an inner mutex, no need for user to add it artificially.

[Altera_Forum]

OK. The Mailbox supposedly is similar to a one stage FiFO. A FiFo will need more resources and offer a much higher transfer speed. 

 BTW.: regarding shared memory: If possible you should restrict the non-Linux coprocessor CPU to just using some tightly coupled memory, Sharing memory via the Avalon but will eat up a lot of hardware resources and slow down the (necessarily very frequent) RAM accesses of the Linux-processor greatly.   -Michael