EMIF using AXI4 Interface for Controller in DDR4

[pdewanga]

Hi team,  

I am trying to connect the emif ctrl_avmm Interface with the AXI Bridge. There are some warning in the system message which I could not get rid off, Also there are error while doing synthesis. Am I doing anything wrong here?  Please correct me with the correct list of IP required to do the task.

Regards,

Piyush

[sstrell]

They're just warnings.  You can ignore them if that's what you want to do.  It would be more useful to know what the synthesis errors are.

[pdewanga]

Hi, 

Little correction, I am able to Generate the HDL but not the Testbench System out of this connection I made (attaching the screenshot).

My question are as follows:

Que.1 how to simulate this configuration of emif+axi_bridge in the Simulation setup?

Que.2 Are any BUS Functional model available for DDR4 SODIMM and where to get it?
Que.3 Is this correct way to create the AXI4 to avalon transaction for ctrl_amm for emif ?

please suggests your inputs.

Thanks 

Piyush

[AdzimZM_Intel]

Hi Piyush,

For EMIF IP, the example design can be generated with traffic generator module to simulate the design.

The example design will only available in avalon interface connection.

To connect the EMIF IP into AXI4 interface, you may need to have an avalon to axi bridge.

This can be done by using avalon bridge to axi bridge then export the axi interface.

For the errors that you are facing, try to use reset controller and clock controller IP and the EMIF IP should use a dedicated PLL clock for reference clock.

Regards,

Adzim