Quartus Prime Pro 24.1 RAM Inference problems

[ELIT1]

When trying to infer Block-RAM from the attached System Verilog code

the following problems occurred:

1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory block,

when 'rd_outcken' input not used or connected in parent module to constant "1'b1" - out registers are packed to memory block.

2 - the output of an additional and-gate ('wr_enbl' & 'wr_cken') is connected to the 'PORTAWE' inputs of memory blocks ('wr_cken' also connected to 'ENA0' input of memory blocks).

In my opinion, 'wr_enbl' must be direct connected to 'PORTAWE' inputs of memory blocks, without and-gate, the necessary logic is inside memory blocks.

How can you avoid these problems?

Thanks

[sstrell]

There is no "rd_outcken" signal in the memory blocks so that has to get implemented in a separate register, as you note.

Similar issue on the write side: there is no "wr_cken" signal for the memory blocks, so it has to add an AND gate up front.

https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/simple-dual-port-dual-clock-synchronous-ram.html

[ELIT1]

Hi.

Altera memory blocks have 4 clock enable inputs:
clocken0, clocken1, clocken2, clocken3
and 6 parameters:
clock_enable_input_a, clock_enable_output_a,
clock_enable_input_b, clock_enable_output_b,
clock_enable_core_a, clock_enable_core_b.

By setting these parameters: "BYPASS" / "NORMAL" / “ALTERNATE” / “USE_INPUT_CLKEN” -

determines the connection and use of clock enable inputs.

Please see the attached file created by Quartus Prime Pro 24.1 IP PARAMETERS EDITOR.

I want to have a synthesizable RTL equivalent.

Thanks,

    ELIT1

[Kenny_Tan]

Give me some time to look into the design, I will get back to you soon.

[Kenny_Tan]

Hi, I manage to download your design to take a look.

One way to understand what are the RAM supported setting is by pulling out the IP from the IP catalog. Set whatever setting that you want and generate out the IP. From there, you can copy out the generated output content of the IP to your design to see what is actually supported.

I attached a screenshot for you to refer. Thanks

[Kenny_Tan]

Screenshot attached

[Kenny_Tan]

Hi,

Not sure if you have further question on this? If no, we shall close this forum thread.

Thanks,

Best regards,

Kenny Tan

[ELIT1]

Hi,

I will continue to use RAM, created by Quartus Prime Pro 24.1 IP PARAMETERS EDITOR.

Please, close this thread.

Thanks,

ELIT1

[Kenny_Tan]

Thanks you for your feedback,

Just take note: the IP editor that you created, will generated some file. This file you can use it as verilog file if you wish to do that. But general advise is to use the .ip file as it is more clean and easier to debug for your whole design. We shall close the thread, thanks again.

[Kenny_Tan]

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