Dear Intel Solid State Drives Community!
I have a question regarding https://ark.intel.com/products/88735/Intel-SSD-DC-P3608-Series-4_0TB-12-Height-PCIe-3_0-x8-20nm-MLC Intel SSD DC P3608 4Tb max payload size. I'm going to use this particular SSD in the system with https://ark.intel.com/ru/products/91317/Intel-Xeon-Processor-E5-2699-v4-55M-Cache-2_20-GHz Intel® Xeon® Processor E5-2699 v4 and a custom FPGA board, and I'd like to estimate which payload size I will have in the system (I mean, PCIe tree with Xeon as a Root Complex), so I can build a firmware for the FPGA according on the actual payload size value set by the BIOS. On the SSD page I couldn't find any information clarifying possible payload sizes.
We understand you would like to know the payload size for the Intel® SSD DC P3608 4TB.
First, we'd like to know if by max payload size you mean to variable sector size, you can check this in the https://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-dc-p3608-spe... following link (Page 15).
If not, please let us have more details about it.
There is another link that could be useful for you, please http://archive.techarp.com/showFreeBOG6509.html?lang=0&bogno=385 access it here.
We'll be waiting for your response on this one as we would like to provide you with the information you need for your purpose.
By max payload size I mean value of the "Max_Payload_Size Supported" register in the NVM Express Specification Rev. 1.1 October 11, 2012, p.28, table "2.5.3 Offset PXCAP + 4h: PXDCAP – PCI Express Device Capabilities".
Second link is quite helpful, thank you! It conforms to the information that I found earlier. On this page it says "If that device only supports a maximum TLP payload size of 512 bytes, the motherboard chipset will communicate with it with a maximum TLP payload size of 512 bytes, even if you set this BIOS feature to 4096". So I'm trying to determine a possible value for the maximum TLP payload size of the entire PCIe tree set by the BIOS in my system. As I have no previous experience with the PCIe, I'd like to begin with some determined parameters, so debugging of a firmware on the FPGA board will be a little bit easy.
Thanks for the reply and explanation.
At this point, we would like to engage additional resources in order to provide you with the best response possible.
We will keep you updated once we have the response.
We have a response to your inquiry from our engineering department, basically, we restrict the Max Payload size to 256B on our ASICs.
If an intermediary component is of smaller MPS size (EgL 128B), BIOS has to restrict the E2E traffic to 128B, even though the endpoint is 256B
Please let us know if this information is what you needed and if in case of further assistance just let us know.
You're very welcome, we're always glad to be of assistance. If there is anything else we can help you with, please don't hesitate to contact us again.