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Cyclone V ALTLVDS TX to RX Transceiver

Cyclone V ALTLVDS TX to RX Transceiver Using Qsys Avalon Data Pattern Generator and Transceiver Toolkit


This wiki page is dedicated towards users that would like an example using:

  • Cyclone V
  • TerasIC Cyclone V GX Starter Development Board
  • Qsys
  • Transceiver Toolkit
  • System Console

This design can also be used to save TX power in Cyclone V. If a user needs to run at a lower bit rate that can be supported by LVDS rather than transceiver TX, they can realize lower power using this example.

This design in this example was adapted from the design here:

The 4 transceiver design example that comes with the TerasIC Cyclone V GX Starter kit was merged into the above design. The transceiver design was adjusted down to operate at 625Mb/s.

Design Example

The following qar file contains the design example.


Hardware Used

This example runs on the TerasIC Cyclone V GX Starter board.

TerasIC Cyclone V-GX Starter Kit


Hardware Setup

Here is a picture of the setup


The board plugged into the TerasIC Cyclone V GX Starter board is a TerasIC HSMC XTS daughter board and uses SMA loopback cables.

TerasIC HSMC XTS Daughter Board


On the TerasIC HSMC-XTS card, the CLKOUT_2 P/N SMAs are connected to the HSMC-RX0 P/N SMAs. The CLKOUT_2 signals are the ALTLVDS_TX pair and the HSMC-RX0 signals are the transceiver RX pair.

  • NOTE: There are DC blocks on the inputs to the transceiver to make sure only AC signals are passed to the transceiver RX side.

Design Description

After downloading the design example and opening in Quartus, review the top level of the hierarchy, altlvds_C5_serial_link.v. This file contains instantiations for the following items that were integral in making this example function:

  • Qsys Avalon Data Pattern Generator
  • Qsys Transceivers
  • TX PLL
  • Management PLL

There are links to documentation in the top level code to assist in understanding.

In addition, there is miscellaneous logic for the following:

  • Switch and key debounce
  • Counters
  • Convert 40 bit streaming Avalon interface to 10-bit ALTLVDS TX and RX interfaces

Qsys Avalon Data Pattern Generator and Data Pattern Checker

For the purposes of this example, only the data pattern generator is applicable since the RX transceiver will be used to check the data.

The following is a picture of the Qsys design used for this example. The design name is pattern_gen_check.qsys.



Notice that the Qsys design contains two data pattern generators and checkers. The *_0 generator and checker have a FIFO in between and were used to understand the register mapping for each. The System Console commands used are based on the memory maps of both the generator and checker (with address offset shown in Qsys).

Link to the embedded IP User's guide. Refer to page 34-5. "Avalon Streaming Data Pattern Generator and Checker Cores -> Register Maps"

Altera Embedded IP Users Guide

The second set of pattern generators and checkers (*_LVDS_SERDES) are used to send and receive data to/from the ALTLVDS_TX and ALTLVDS_RX IP blocks instantiated at the top level of the project, altlvds_C5_serial_link.v. The Avalon streaming interfaces on the data pattern generator and checker were exported to the Qsys design port map, the top level of pattern_gen_check.qsys.

The top level project file, altlvds_C5_serial_link.v, instantiates pattern_gen_check.v that was generated from Qsys. The top level project, altlvds_C5_serial_link.v, contains basic logic to allow interface to the Avalon Streaming ports that were exported in Qsys to the top level.

The Avalon streaming interface for the data pattern generator and checker is 40 bits wide. The width is converted to 10-bits for the ALTLVDS TX and RX IP at the top level, altlvds_C5_serial_link.v.

After downloading the sof file to the TerasIC board, System Console can be used to start the data pattern generator and insert errors in the TX path. The System Console section of this wiki page has examples that show how to start the data pattern generator and inject errors. The transceiver toolkit will be used to check the data integrity on the RX side.

Qsys Transceivers

The transceivers are implemented in Qsys. Top level Qsys file c5g_xcvr_qsys.qsys calls a lower level Qsys file, C5_HSMC_XCVR that contains the actual transceiver IP. Note that NIOSII is contained in the design. For this example, only transceiver HSMC_XCVR_1 RX side is used to verify traffic. NIOSII is not used in this example.

System Console

Open the transceiver toolkit which runs using system console. Make sure the sof file of this example is linked. It is linked if you are able to see all 4 transceivers in the design. Click on the "Receiver Channels" tab. Make sure the first receiver channel is highlighted (RX_HSMC_XCVR_0_xcvr_custom_phy_0_address_2). Click on the button "Control Receiver Channel". Change the test pattern to PRBS31.

Now, to start the data pattern generator in Qsys that will send data to the ALTLDVDS_TX. Issue the following commands in the Transceiver toolkit (System Console) window.

% get_service_paths master
% set mm [ lindex [ get_service_paths master ] 1]
% open_service master $mm
% master_write_32 $mm 0x4 0x8
% master_write_32 $mm 0x0 0x1
% master_write_32 $mm 0x8 0x1
% master_write_32 $mm 0x8 0x1
% master_write_32 $mm 0x8 0x1
% master_write_32 $mm 0x8 0x1
% master_write_32 $mm 0x8 0x1

The above will open the JTAG to Avalon master that is within the Qsys module that contains the Avalon Data Pattern Generator. The master write commands are then used to change the data pattern to PRBS31, start traffic, and then inject 5 errors. A screenshot below is what you should see.



Version history
Last update:
‎07-10-2020 09:10 AM
Updated by: