cancel
Showing results for 
Search instead for 
Did you mean: 
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
834 Discussions

Implementing Loopback in Triple-Speed Ethernet Designs

Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers


Application Note

 Please refer to AN633 - Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers Design on Altera Support Webpage:

    www/support/ip/interface-protocols/ips-inp-tse.html


What's New?

  1. Upgrade to ACDS 12.0sp2
  2. Open source CRC-32 Ethernet Compiler
  3. Upgrade SOPC to Qsys


Download Reference Designs

 Design file for Arria II GX Device

           Download here

 Design file for Stratix IV GX Device

          Download here


Notes

Since the file and folders are rearranged, the path and file name might be changed.  

Attachments
Version history
Last update:
‎06-27-2019 05:08 PM
Updated by:
Contributors