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Multiple Memory interface Using Uniphy

Multiple Memory interface Using Uniphy

Last Major Update

Initial Release – Sept 2011 – Stratix V DDR3 SDRAM 450MHz, Quartus II v11.0, Multiple Memory interface Using Uniphy.

Design Overview

This design is created for evaluation purpose only.In future quartus release, the design will be updated targetting on same memory protocols for resources sharing implementation. This design has passed timing requirement and does not target any hardware design board. This tutorial describes how to use the design flow to implement a design with multiple memory interfaces, using two 16-bit wide, 1-GB Micron MT41J64M16LA-15E 667-MHz DDR3 SDRAM controllers with UniPHY interface. This tutorial also provides some recommended settings to simplify the design. In this tutorial, you implement two DDR3 SDRAM controllers, operating at the same frequency of 450 MHz and using the UniPHY IP, in a single Stratix V device. This implementation requires device resource sharing, such as delay-locked loops (DLLs), phase-locked loops (PLLs), and on-chip termination (OCT) control blocks, and may require extra steps to create the interfaces in a Quartus II project.The design example in this tutorial uses a Stratix V device with two DDR3 SDRAM memory components with timing closure and RTL simulation verification on the master memory.

 

Design Specifications

The table below lists the specifications for this design: 

AttributeSpecification
Quartus versionQuartusII v11.0
FPGA5SGXMA7K2F40C2 
Memory deviceDDR3 SRAM ( Micron MT41J64M16LA-15E)
Memory speed667MHz
Memory topologyX16-bit, DDR3 SRAM component
IP used DDR3 SRAM Controller with UniPHY IP


Lab Steps

The lab uses Quartus II v11.0 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features. 

Three files have been pre-designed for this lab to save time.

• A top level design for multiple memory interface (sv_multiple_ddr3.v)

• A QuartusII IP file (core2_example.qip)

• A text file with file name and location required for simulation (testbench.txt)

Two Quartus archive available with one for the final project and the other for simulation design are also included for reference.

Files for this lab are located in this zip file -Emi_multiple_ddr3_sv.zip‎

Create a new folder for the project and place the files in it.


Design Generation

1. Generating a Multiple Memory Interface with UniPHY

Start Quartus, open MegaWizard Plug-In Manager and create a new variation

• In the Megawizard GUI, set device family to be Stratix V

• The IP is located under the folders Interfaces/External Memory/DDR3, choose DDR3 SDRAM Controller with UniPHY v11.0

• If your license for ModelSim can not support multiple HDL languages then choose verilog as output file type

• For the name of the output file, browse to the folder you created above, give the instance the name Type core1 for the master and core2 for the slave.

 

2. Parameterizing the Controllers   

To parameterize the master or slave controller to interface with a 16-bit wide DDR3 SDRAM interface, perform the following steps:

1. In the Presets list, select MT41J64M16LA-15E and click Apply

2. In the PHY Settings tab, under Clocks, for Memory clock frequency, type 450 MHz as the system frequency.

3. For PLL reference clock frequency, type 100 MHz to match the on-board oscillator.

4. For Full or half rate on Avalon-MM interface, select Half. This option allows you to choose between the full-rate and half-rate controller, and define the

busdata width between the controller and the PHY.

5. Under Advanced PHY Settings, turn on Advanced clock phase control.

6. For Additional address and command clock phase, type -22.50 for the master controller (core1), and 0 for the slave controller (core2).

7. For Supply Voltage, select 1.5-V DDR3.

8. For PLL sharing mode, DLL sharing mode, and OCT sharing mode, select Master for the master controller (core1) and select Slave for the slave

controller (core2).

9. In the Memory Parameters tab, for Total interface width, type 16.

10. Under Memory Topology, turn on Fly-by topology.

11. Under Memory Initialization Options, for Memory CAS latency setting, select 8.

12. For Output drive strength setting, select RZQ/7.

13. For ODT Rtt nominal value, select RZQ/4.

14. For Memory write CAS latency setting, select 6.

15. For Dynamic ODT (Rtt_WR) value, select RZQ/4.

16. In the Board Settings tab, for setup and hold derating, and board skews, use Altera’s default settings.

17. In the Controller Settings tab, under Avalon Interface, for Maximum Avalon-MM burst length, specify the burst length based on the burst count sent from

the core fabric. For example, if your system generates up to 64 beats, then select 64.

18. In the Diagnostics tab, under Simulation Options, for Auto-calibration mode, select Quick initialization and skip calibration. This option allows you

to skip memory calibration during simulation and decrease simulation time.

19. Click Finish to generate your MegaCore function variation. The MegaWizard Plug-In Manager generates all the files necessary for your DDR3 SDRAM

controller with UniPHY, and an example top-level design, which you may use to test or verify the board operation.

20. Click Exit to close the MegaWizard Plug-In Manager after you have reviewed the generation report.


3. Adding Constraints

A. Adding PLL Sharing Constraint

1. On the File menu, click Open.

2. Browse to core2_example_design\example_project\core2_example\submodules\core2_example_if0_p0_timing.tcl. and click Open.

3. Locate the following PLL clock assignments:

set master_corename "_MASTER_CORE_"

set master_instname "_MASTER_INST_"

 

and change the master instance and core names to match the names you specify in your design, for example:

set master_corename “core1_example_if0_p0”

set master_instname “if02|p0”

 

4. Click Save.

5. Browse to core2_example_design\example_project\core2_example\submodules\core2_example_if0_p0_report_timing_core.tcl and click Open.

6. Locate the following assignments:

set dqs_periphery_node${inst}|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[${leveling_delay_chain_number}].ubidir_dq_dqs|

altdq_dqs2_inst|thechain|clkinif {$isdmpin == 1} {set dq_periphery_node${inst}|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddi o

[${leveling_delay_chain_number_dq}].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin} else {set dq_periphery_node${inst}|controller_phy_inst|

memphy_top_inst|umemphy|uio_pads|dq_ddio[${leveling_delay_chain_number_dq}].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin}

 

and change to the following:

set dqs_periphery_node*|*|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[${leveling_delay_chain_number}].ubidir_dq_dqs|

altdq_dqs2_inst|thechain|clkinif {$isdmpin == 1} {set dq_periphery_node*|*|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[${

leveling_delay_chain_number_dq}].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin} else {set dq_periphery_node*|*|controller_phy_inst|

memphy_top_inst|umemphy|uio_pads|dq_ddio[${leveling_delay_chain_number_dq}].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin}

 

7. Click Save.

 

B:Setting Pins

Set the unused pin and device voltage correctly before adding the constraint and pin assignment. Perform the following steps to set the device voltage and

unused pins:

1. In the Assignments list, select Device and click Device and Pin Options.

2. Click the Unused Pins tab, and for Reserve all unused pins select As input tri-stated with weak pull-up.

3. Click the Voltage tab, and for Default I/O standard select 1.5 V.

4. Click OK.


C: Adding Example Project

Add the example project files to your project, by performing the following steps:

1. On the Project menu, click Add/Remove Files in Project.

2. Browse to the <variation_name>_example_design\example_design directory.

3. Select <variation_name>_example.qip for the master DDR3 SDRAM component, and click Open.

4. Click OK.

5. Open <variation_name>_example.qip for the slave DDR3 SDRAM component, and remove the duplicate file in the slave DDR3 SDRAM component,or

use the Altera-provided .qip file.

6. Click Save.


D: Adding Pin and DQ Group Assignments

Run the core1_example_if0_p0_pin_assignment.tcl and core2_example_if0_p0_pin_assignment.tcl scripts to add the pins, I/O standards, and DQ group

assignments to the design example. To run the pin assignment scripts, perform the following steps:

1. On the Processing menu, point to Start and then click Start Analysis & Synthesis.

2. In the Tools menu, click Tcl Scripts.

3. Locate the core1_example_if0_p0_pin_assignments.tcl file.

4. Click Run.

5. Repeat steps 1 to 4 to locate and run the core2_example_if0_p0_pin_assignments.tcl script.


E: Assigning Pins

The pin assignments for this example design does not matters as it does not target a specified board.

 

4. Compiling Design and Verifying Timing 

To compile the design, on the Processing menu, click Start Compilation. After successfully compiling the design, the Quartus II software automatically runs the

verified timing script of the master DDR3 SDRAM memory, <variation_name>_p0_report_timing.tcl, which produces a timing margin report for the

design together with the compilation report. The report timing script performs the following tasks:

1. Creates a timing netlist.

2. Reads the <variation_name>.sdc file.

3. Updates the timing netlist. You can also obtain the timing report by running the report timing script in the TimeQuest timing analyzer. To obtain the timing

report in the TimeQuest Timing Analyzer window, perform the following steps:

1. In the Quartus II software, on the Tools menu, click TimeQuest Timing Analyzer.

2. On the Tasks pane, double-click Report DDR which automatically runs Update Timing Netlist, Create Timing Netlist, and Read SDC. This command

subsequently executes the report timing script to generate the timing margin report. The results are the same as the Quartus II software results.


5. Performing RTL Simulation

This section describes RTL simulation. The Quartus II software automatically generates a RTL simulation project file for both the master and slave DDR3 SDRAM instances with UniPHY. You can obtain the RTL simulation project file from the <variation_name>_example_design\simulation folder. When creating a multiple-memory interface design, you must modify the testbench to perform functional simulation. You can create a testbench that combines all the memory interfaces in the design or simulate the master component. You cannot use the RTL simulation project file for a stand-alone slave component, because the slave component requires you to provide a master interface. You can use this project file to verify your design or to create an RTL simulation on the top-level project file.


To run the RTL simulation with NativeLink, follow these steps:

1. Set the absolute path to your third-party simulator executable, by performing the following steps:

  • a. On the Tools menu, click Options.
  • b. In the Category list, select EDA Tools Options and set the default path for ModelSim-Altera to C:\<version>\modelsim_ae\win32aloem.
  • c. Click OK.

2. On the Assignments menu, click Settings.

3. In the Category list, expand EDA Tool Settings and click Simulation.

4. Under Tool name, select ModelSim-Altera.

5. Under NativeLink settings, select Compile test bench and click Test Benches.

6. Click New.

7. In the Edit Test Bench Settings dialog box, perform the following steps:

  • a. For Test bench name, type core1_example_sim for the master DDR3 SDRAM.
  • b. For Top level module in test bench, type core1_example_sim_tb for the master DDR3 SDRAM.
  • c. Under Simulation period, select Run simulation until all vector stimuli are used.
  • d. In the Test bench files field, include the testbench files listed in the testbench.txt file from the emi_multiple_ddr3_sv.zip folder.
  • e. Click OK.

8. To elaborate your design, on the Processing menu, point to Start and click Start Analysis & Elaboration.

9. On the Tools menu, point to the Run EDA Simulation Tool and click EDA RTL Simulation. This step creates the \simulation directory in your project

directory and a script that compiles all necessary files and runs the simulation.

10. Add all the signal to the wave window and click Run all to run the simulation.



Notes/Comments

For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.


Update History

Initial Release – Sept 2011 – Stratix V DDR3 SDRAM 450MHz, Quartus II v11.0, Multiple Memory interface Using Uniphy 

See Also

1. List of designs using Altera External Memory IP


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

UniPHY,DDR3 SRAM, Design Example, External Memory , Stratix V

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Last update:
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