This simple example demonstrates the use of Altera's read-only zip filing system. The example includes a zip file (.zip file) containing three text files. The filing system is first programmed into the hardware design's common flash interface (CFI) compliant flash using the Nios II Flash programmer. When you run the application it opens two of the text files in the filing system, then prints them to STDOUT.
Source code for example application
Create-this scripts for app and bsp
NOTE: If you are using Nios II EDS v7.2 or earlier then this design example is already contained in the example folder of your installation.
The following steps are for Nios II EDS v8.0 and later.
Download the zip file.
Copy the hardware example design for your board from the Nios II EDS installation (c:\altera\<version_number>\nios2eds\examples\<verilog or vhdl>) to your working directory.
Extract the contents of the zip file to the software application directory for the hardware project in your working directory. For example if you are using the standard verilog hardware design in the Nios II Development Kit, Cylcone II Edition, extract the zip file to \<work_directory>\niosII_cycloneII_2c35\standard\software_examples\app.
Create a new folder called "hal_zipfs" in the bsp directory under the hardware example.
Cut and paste the create-this-bsp file from the /app dir to the hal_zipfs directory.