I have encountered many problems in order to understand how to correctly set parameter for bursting using the frame buffer (or deinterlacer).
in an427, they (altera) set a port width of 128 because of the half data rate controller (wich quadruples the DDR sdram witdh). So, 64 bits-witdh are for the write fifo, and 64 for the read fifo.
So, why burst size target is set to 32?
Now, i am trying to use a similar system in my vip, but instead of a DDR I have only a SDR with a data width of 16 bits,and the ip of the controller Altera provides works fine only with a clock of 50Mhz.
I've empirically found out that wit 64-32-16-32-16 bits, it seems to work properly.
But honestly, I didn't understand WHY this settings are correct.
Could any one help me to understand why?
