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Tozpen50
Beginner
381 Views

How the data is transferred by TX port of Avalon-MM PCIe

Hi,

 

We are developing a PCIe application with SGDMA DMA controller. The SGDMA mm_write port (128 bits wide) is connected to the slave TX port of Avalon-MM V PCIe core. The SGDMA 'Burst Enable' option set to 'enable' and 'Maximum Burst Count' set to 16. After initialization the SGDMA generates burst write requests to the TX port with size of 16. The 256 B payload packet is transferred by PCIe.

 

From datasheet of PCIe core:

'The Avalon-MM bridge accepts Avalon-MM burst write requests with a burst size of up to 512 bytes at the Avalon-MM TX slave interface. The Avalon-MM bridge converts the write requests to one or more PCI

Express write packets with 32– or 64-bit addresses based on the address translation configuration, the request address, and the maximum payload size.'

 

Maybe somebody could explain me the following questions.

 

1. When is the PCI Express TLP packet sent by PCIe core to host memory? After writting to TX port maximum payload size? The 'Maximum pyload size' is set to 256 B.

 

2. When is the TLP packet sent if short bursts or single Avalon writes to TX are generated? After writing maximum payload? Or maybe it is any possibility to generate and send a short TLP packet with size less than maximum payload.

 

3.

An example:

- first Avalon write to the TX port: burst count = 4, write address = 0x1000000

- the second Avalon write: burst count = 2, write address = 0x1000040

- the third Avalon write: burst count = 16, write address = 0x2000000

 

The first and the second transfer in one PCI express TLP packet starting with address 0x1000000? In one short 96 B packet? Or maybe more data is required to fit 256 B TLP?

What about of the third write? In separate TLP packet starting with address 0x2000000?

 

With regards

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3 Replies
SengKok_L_Intel
Moderator
64 Views

Hi, For TXS port, this is a single Dword port. If you are referring to the Maximum transfer size, the data is broken into multiple PCIe TLP base on the MPS (Maximum transfer size). For example, a 4KB read requires, will break into 8 requests if the MPS is 512 bytes. If the data size is less than MPS, it just transfer by using 1 TLP, no padding required. Regards -SK
Tozpen50
Beginner
64 Views

 

Hi,

The TX Avalon-MM slave port of Avalon-MM Cyclone V Hard IP core has burst capabilities. The TxsBurstCount signal allows bursts limited to 512 B.

My questions are related to how the V PCIe core translates write requests from interconnect fabric into PCI Express memory write packets. The fabric as a bursting Avalon-MM master is connected to the slave TX port. The master sets starting addres and burst count at the beginning of Avalon transfer. Next data are written until the end of this burst. It is expected that the data will be sent in PCIe memory write packet. 

The PCI Express TLP header has 'Length' field specifying the length of data payload. According to PCI Express specification, TLP payload size can be less or equals to the maximum value. 

 

It is important when PCIe packet is generated with reference to the end of Avalon burst write.

If FPGA fabric want to write e.g. 64 bytes of data, which is less than the maximum value for TLP data payload, it can generate one Avalon-MM write transfer with burst count for 64 bytes? No padding is required?

 

SengKok_L_Intel
Moderator
64 Views

​Hi,

 

Thank you for clarifying that you are using AVMM Cyclone V Hard IP. By referring to the user guide, the txs_burstcount, the count unit is the amount of data that is transferred in a single cycle, the width of the write/read data can be 64 or 128 bits. There is a txs_byteenable port, so the padding from the user logic is not required as i can see.

 

Regards -SK

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