How to configure the dsp ip core to make a 16-bit 3-input adder with good timing

[Jianing1]

Hi, I want to use DSP to do the internet checksum offloading. I want to do a+b+c (16 bits) in one clock and I am using Agilex7 AGFB023R25A2E2V.

I selected Native Floating Point DSP and configured to "Sum of two FP16 multiplication with FP32 addition mode" using  "fp16_mult_top_a*fp16_mult_top_b(16'b1) + fp16_mult_bot_a*fp16_mult_bot_b(16'b1) + fp32_adder_a".

However, the timing of my project changed from 0 ns to -2 ns with about 18 DSP enabled. Do you know how to configure the DSP to have a better timing performance? Do I have a better choice for the IP core?

[Kshitij_Intel]

Hi,

Please add the pipeline registers. If still not solved, please share your project I will have a look once.

Thank you,

Kshitij Goel

[FvM]

Unfortunately you don't even tell the intended clock frequency, so we can't determine if 1 clock latency could be feasible. Apparently it's not.

Don't see that internet checksum uses float numbers.

[Kshitij_Intel]

Hi,

Best you use the template available within the Quartus for multiplication and addition. Sharing the screenshot below.

The Maximum frequency of operation depends on the multiple factors and configuration and pipelining and device speed grade and Quartus version as well.

Language Templates

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel