max data rate calculation for NIOS II

Altera_Forum · ‎03-12-2009

Hi,

i want to know how to calculate the max data rate that a NIOS II processor can read from a PIO interface. As far as i understand, i think it depends on core frequency of NIOS II and also may be the no of instruction cycles it takes to read the PIO. If i'm wrong please correct me.. Looking forward for a fast reply..

Altera_Forum · ‎03-24-2009

HI, did you get any infomation on this?

Altera_Forum · ‎03-30-2009

No not yet... If you have any idea pls let me know...Your help will be appreciated...

Altera_Forum · ‎04-14-2009

It depends on a few factors, and I'm not sure you can get a constant value for this.

Like you mentioned, Nios II frequency and instruction cycles play a role.

You can also look at the latency from the PIO, which I believe is 1 cycle.

Next is the system architecture. The arbitration within the bus will affect the latency of data coming back.

Your best bet is to use tightly-coupled memories for the CPU data and instruction, have direct connections to your PIO without going through bridges, etc.