FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5287 Discussions

Critical Warning: DDR Timing requirements not met

Yogesh
Novice
370 Views

I have built a FPGA design with NIOS. But there are some timing warnings as below:

Critical Warning: DDR Timing requirements not met

Overwriting existing clock: <Clock Name>

When I was debugging the same on stp . I could see read_request and address is being sent correctly by the custom RTL IP. But I am not able to receive i_ddr_data_valid signal from ddr. Data seems to correct on i_ddr_read_data of DDR.

 

How should I go about solving this issue?

0 Kudos
3 Replies
yoichiK_intel
Employee
352 Views

Hi 

Since you are receiving the DDT timing critical warning do you see the timing violation in Timing Analysis report ? 

Yogesh
Novice
350 Views

Yes , There are about 12 paths violated inside SDRAM.

 

yoichiK_intel
Employee
342 Views

then why can not you close the timing ?

Reply