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FPGA Evaluation and Development Kits

Device Tree (.dts) files

greenlantern01
New Contributor I
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I am currently using DE10 Standard FPGA for my project. I used the GHRD project and edited it according to my needs (added/removed a few qsys components).

 

Do I need to manually edit the dts file or is there a way to generate dts files? 

 

Kindly let me know.

 

Regards

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aikeu
Employee
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Hi greenlantern01,


For existing components added into your FPGA design, you will need to consider some settings indication in the device tree. Example for 3-wire spi added into the device tree node, it should indicate the specific connected address in your system design which can be viewed from quartus platform designer. Besides that, the driver being used for that particular component, referring to the compatible part of the device tree node. Other than that will be the normal settings for the IP itself.

Example:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086095.html


You will need to target the specific component in your design in order to consider how the device tree node should be set accordingly. Each component device tree node settings can be very different and is also application specific. Recommend to find reference from other related working projects or the documentation for a particular ip may mentioned how it's ip device tree can be set.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
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Hi greenlantern01,

 

May I know which component which you intend to add or removed?

some component need to be defined in the device tree for it to work in uboot or linux kernel. Some of the components for HPS side and some for FPGA side.

Example for Cyclone V Uboot, the device tree has considered some of the components:

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2023.10/arch/arm/dts/socfpga.dtsi

 

 

Thanks.

Regards,

Aik Eu

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greenlantern01
New Contributor I
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Hello,

 

I have HPS, On-Chip Memory, Modular Scatter Gather DMA, SPI (3 wire serial) and "System and SDRAM Clocks for DE-Series Boards" components in my Qsys.

 

Thanks

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aikeu
Employee
118 Views

Hi greenlantern01,


For existing components added into your FPGA design, you will need to consider some settings indication in the device tree. Example for 3-wire spi added into the device tree node, it should indicate the specific connected address in your system design which can be viewed from quartus platform designer. Besides that, the driver being used for that particular component, referring to the compatible part of the device tree node. Other than that will be the normal settings for the IP itself.

Example:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086095.html


You will need to target the specific component in your design in order to consider how the device tree node should be set accordingly. Each component device tree node settings can be very different and is also application specific. Recommend to find reference from other related working projects or the documentation for a particular ip may mentioned how it's ip device tree can be set.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
80 Views

Hi greenlantern01,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thanks.

Regards,

Aik Eu


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