Hi, We need to design hardware for MAX10M04DAF256C8G FPGA with Ethercat communication. Since I am new to both FPGA and Ethercat, it will be great if you could suggest me how to kick start this task. Thanks & Regards, Sunil Suvarna.

[AnandRaj_S_Intel]

Hi Sunil,

For hardware design, you have to refer to

1. pin connection guidelines of the specific device
2. Signal Integrity Design Guidelines
3. Device handbook other guidelines.
4. pinout file for the device

And also refer schematic & .brd from Evaluation or development kit.

Also, design the HDL as per requirement and see Quartus tools compiles and fits design successfully.

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/max-10/m10_guidelines.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_sidg.pdf

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/schematic-review-ws.html

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand