Hi, copied below is from Intel document that indicates that for every 4KB of configuration data, CVP_CREDIT shall be polled, and Stratix 10 CvP reponse can take typically 5 sec to maximum 1 min. What does it mean? Is the 5 sec for every polling of the CVP_CREDIT for every 4KB? If so, and if the .rbf file is 32MB, the entire process could take as long as (32MB/4K) * 5sec = 8K * 5 sec that is more than 20 hours! Please clarify what the 5sec and 1min mean exactly. Thanks.
----- copied from Intel document --------
When you poll the CVP_CREDIT bits from the CvP credit register, you must write
the next 4KB of fabric configuration data to the CvP data register within 50 ms of
receiving an additional credit. Failure to send the data results in configuration
• The CvP response time is variable and depends on different conditions. The typical
delay time is 5 sec and it is safe to wait till 1 min. So the driver should poll status
in credit register to decide on driver timeout.
Hi, would you clarify what is exactly the response or status update? Is it the response or status update for the availability of the CVP_CREDIT? I try to estimate how long it takes for CvP Update to complete a 32MB .rbf file, the minimum, typical, and the maximum. 32MB is uncompressed. If a compressed .rbf file can be used, how long it would take. Thanks.
Does anyone have experience of CvP Update on Stratix 10? Just from Intel's ug_s10_cvp.pdf and the copies paragraph from the OP, typically for CvP Update of 32MB .rbf it would take (32MB/4KB) * 5 sec / 3600 sec/hour that is more than 10 hours, or maximum 1 min / 5 sec times the typical that is 200 hours!
Polling of the CVP_CREDIT and error status are documented in the Intel document and it seems that they are required. If none of the polling of the CVP_CREDIT and error status is required, Intel may need to update the document. It is questionable why the CPV_CREDIT register exists in the driver flow and if the error status polling is skipped whether the error status in any 4KB transfer will stick to the end of the process.
If both CVP_CREDIT and error status could be skipped, at least the error status at the end of the CvP Update process needs to be polled, and in this case, it will take at least 1 min to find out whether there is any error unless there exists a register bit to indicate that the status is ready. Is there any such register bit?