I'm working with an Arria 10 GX evaluation board. I want to do dynamic reconfiguration of the transceivers.
But I can't find the VCO frequency range for the CMU PLL. In the Arria 10 Transceiver PHY User Guide I found "The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the datasheet."
But in the Arria 10 Device Datasheet I can only find information about the FPLL and the I/O PLL VCO https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_datasheet.p...
Same for the PFD input ranges.
Can someone help me with this?
I know the table, but is not what I'm looking for.
If we take a look at "Intel Arria10 Transceiver PHY User Guide" https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr...,
Figure 174 (page 367), the internal diagram of the CMU PLL. I can deduce the VCO frequency as being VCO = L * M * ref_clk / N
If I take the maximum L, M and input reference clock frequency(800MHz) and bypass N, I get 51.2GHz, this will clearly not the maximum.
From the datasheet/user guide, the maximum VCO frequency(-1 speed-grade) for I/O PLL is 1.6GHz for ATX PLL I found: "For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2)".
The PFD is ranges are very important as well.
I can get some ranges from the Arria 10 Transceivers CMU PLL IP for what I need.
Do you have other suggestions to get a more generic min-max ranges for VCO and PFD frequencies?