Synchronizing Asynchronous Resets / Reset Design

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Synchronizing Asynchronous Resets / Reset Design

Synchronizing Asynchronous Resets / Reset Design



Synchronizing asynchronous resets.

In many FPGA/CPLD designs, there is not much thought put into resets, and a simple asynchronous reset from the board is brought into the FPGA and simply resets all of the registers. This may work in many applications, but if there are circuits in your design that start running immediately upon release of the reset, your circuit may behave incorrecltly. This type of failure is very hard to catch in the lab as the relationship of the clock and the reset have to align such that the problem is exhibited.

Below is one way to synchronize a reset such that the reset is asserted asynchronously (your circuit will go into reset without a clock), but the reset is removed synchronous to the clock (the circuit comes out of reset synchronously on a clock edge). Quartus' Timequest timing analyzer tool will analyze this path with recovery/removal analysis. For more information on Timequest, check out the  TimeQuest User Guide and the Altera Timequest resource page 


Webex recoding showing what can happen with a pure asynchronous reset, and how to synchronize the reset:



Asynchronous reset- Asynch_reset.JPG (Click here for image)



Synchronizing the asynchronous reset- Synchronized_reset.JPG (Click here for image)



Timing Diagram of the synchronized reset- Timing_diagram.JPG (Click here for image)


Version history
Last update:
‎12-21-2022 03:06 PM
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