- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I am wondering if anyone knows an efficient parallel prefix sum OpenCL implementation for FPGA. I am currently using the one at CLPP , but it is extremely slow. I guess it makes sense since it was developed earlier for GPU. Anyone knows an open source parallel prefix sum optimized for FPGA? Thanks
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
If you have the CUDA code for the prefix sum , then you can convert it to DPC++ and then try to compile the DPC++ code for FPGA.
Thanks and Regards
Anil
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Please let us know if the previous suggestions was helpful.
So that we can treat this issue as closed.
Thanks and Regards
Anil
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page