Avalon Verification IP example avlmm_1x1_vhdl not working in Questa Intel FPGA Edition

[powARman]

Hi,

I encountered some issues with the Avalon-MM BFM we use in simulations after upgrading our project to Quartus 21.1. The BFM is not behaving as expected, accesses to the bus are not finished.

To verify that this is not an issue of our implementation, I tried running the avlmm_1x1_vhdl example from the Avalon Verification IP Suite both in Modelsim Intel FPGA Edition 2020.1 (part of Quartus Standard 20.1) and Questa Intel FPGA Edition 2021.2 (part of Quartus Prime Standard 21.1). I also tried later Quartus Prime versions, but they include the same version of Questa, so there is no difference in using those.

In Modelsim everything works fine, where in  Questa the access to the BFM are not finished as expected, the simulation just "hangs" during the second access, see screenshots below. The main difference I see is the master_0/events and slave_0/events signal, which is updating every clock cycle in Modelsim, but is updating much less in Questa.

Is this a known issue of Questa? Is there anything to configure to get around this?

Best regards

Andreas

[ShengN_Intel · Accepted solution]

Hi,

Please follow the debug steps below:

1.In the run_simulation.tcl script, add this command set USER_DEFINED_ELAB_OPTIONS -novopt to simulate without optimization.

2.Then, in the command prompt type vsim -suppress 12110 to invoke the Questa simulator GUI.

3.Then, do run_simulation.tcl script again and should see the full complete simulation.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[powARman]

Hi Sheng,

I tried it and it works fine now. Thank You