Cyclone IV external memory design guideline/tutorial

[Altera_Forum]

Hi, 

 i have the cyclone IV EP4CE10 starterkid.   I would like to add now the onboard SDRAM chip to my design. I found lots of information for other devices, but i got more confused. Does anyone know where i can get a reference book or a tutorial design guideline, primary for this device type ?  Cheers, Tim

[Altera_Forum]

I don't see much information on the 4CE10 starter kit. Usually devboards will come with a CD or software that will have a few reference designs that use the main components. 

 The very mininimum you need is a PDF of the pinout, so you can see how to hook up the pins in Quartus.  I'm assuming you want to play with NIOS and get a simple design running, but you need more memory. QSYS in Quartus is where you can stitch a system together, but a 4CE10 is a pretty small device, so stay with the simplest nios processor and then add an SDRAM controler that will work with you SDRAM chip.   You then have to map the QSYS system into your top design and assign all the pins properly.  If you don't want a processor, you can still uses qsys to instantiate a sdram controller. But now you need to hack it and learn Avalon bus structures.  Or you can look up the data sheet for the SDRAM part, and write a simple controller for your specific needs.  All of them are learning opportunities, You may want to look at a Terasic DE0 board. It's a nice little board, and I know they have pretty good reference designs with their kits.  Even if you don't buy a board it could give you ideas looking at their reference designs.   Pete

[Altera_Forum]

Hey Pete, 

 thanks for the detailed answer. We have just the board, the CD is nowhere to be found. Online i found the datasheet with the pinout.  http://www.devboards.de/en/home/boards/product-details/article/db-start-4ce10/  Yes i want to have a simple example where i make use of the onchip sdram device. I decided to instantiate a nios cputogether with a sdram controller. The Quartus project and the qsys system compile well, but Eclipse gives me error messages. Still i think i have  some design errors.   https://www.alteraforum.com/forum/attachment.php?attachmentid=8500   I set up a qsys system using the SDRAM controller. The reset and exception vector of the nios processor are assigned to the sdram. Is the controller i selected correct? I saw that the same was used in the small example from the datasheet. By the way do you know why the addresses in qsys are seperated by a underscore?     In the quartus project i connected all pins from the controller to the fpga pins like i found them in the pinout.  I connected the shifted output to pin 127 of the fpga in order to give a delayed clock signal to the sdram. But is that the way to modify the sdram clock signal?  https://www.alteraforum.com/forum/attachment.php?attachmentid=8501   The datasheet suggested that the  "offset of the ppl" - "t_co" is between -1.0ns and -2.0ns. I didnt find the value for t_co in the compilation report, so i am playing around with the value a bit.    I get four critical warnings of this tpye in quartus: "Critical Warning (332168): The following clock transfers have no clock uncertainty assignment.  For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command."  In the NIOS BSP editor i changed in the linker script all entries to sdram_controller.  When i try to run the simple hello world program i run into the point where the error occurs:  using cable "usb-blaster [usb-0]", device 1, instance 0x00 processor is already paused reading system id at address 0x02011008:   id value was not verified: value was not specified  timestamp value was not verified: value was not specified initializing cpu cache (if present) ok  downloading 01000000 ( 0%) downloading 0100137c (85%) downloaded 5kb in 0.1s   verifying 01000000 ( 0%) verify failed between address 0x1000000 and 0x10010a7 leaving target processor paused  The addresses match partial the sdram module addresses, i think i have a problem with the timing in the sdram module. I read here http://www.alteraforum.com/forum/showthread.php?t=21545  that to solve the problem, i have to add a timing constraints file. Now i will have a look to timing setting, but could you tell me if the design is ok, and if this is the right way to go?  Cheers, Tim