HelloWe have developed a prototype which uses a stratixIII ep3sl50f780c3, but because of a layout problem in PLL powering, only pll TOP1 can be used. The problem is that the program uses an altpll megafunction, and during the compilation (fitter) the altpll is assigned with BOTTOM1 pll. (The only constraints I found is to select Left_right pll or Top_bottom PLL in PLL type, in altpll megafunction). Do you know how to set the PLL in TOP1 position? Thanks,
Hi,Not sure if this will work but can you add a location assignment to the PLL using the assignment editor. The Value should be the location required. For Stratix II something like PLL_1 etc. You'll need to work out the correct location name you require for Stratix III. I have not done this before and I am not sure if it will work as expected! Let me know how you get on Rgds
Yes, location assignment for PLLs in Assignment Editor works, and seems to be necessary in some cases, where the compiler/fitter apparently isn't able to select the correct PLL automaticly, e. g. to drive a dedicated clock output. Here an example for a PLL component instantiated in a design entity timing, instance name pll1.
set_location_assignment PLL_3 -to "timing:pll1|altpll:altpll_component|altpll_mke1:auto_generated"The PLL naming scheme for your device (legal assignments) can be seen in Assignment Editor interactive entry, or learnt from the Quartus report resource section.
Ok, it can be done in assignment editor.I select the instance of my pll, select location, and then write PLL_T1 for the value... easy! Thanks for your help.