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Valued Contributor III
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How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. 

 

However, Quartus is using the DSP blocks for the multiplies and then failing timing specs. This seems like an early stage problem as it starts consuming DSP resources right at the early portions of Analysis & Synthesis. 

 

Is there a way to make Quartus synthesize those constant multiplies short of rewriting the block with shifts and adds by hand? I'm on Quartus 12.1sp1 on Windows 7 64-bit. 

 

Thanks.
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Valued Contributor III

 

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How are these multipliers implemented? Ive also had experience showing that infered mult-add trees wont clock as fast as using megafunctions. And to make it clock faster, LUTs had to be in place over DSP blocks. 

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No tree. Just a pure multiply. Flop->flop->multiply->flop->flop. 

 

TimeQuest critical path shows data arrival path as global clock->DSP block->flop (CLKCTRL_G2->DSP_X70_Y69_N0->FF_X71_Y69_N14) with data required path being global clock->flop (CLKCTRL_G2->FF_X71_Y69_N14). 

 

Don't really see how I can get any cleaner than that ... 

 

I have a ticket open with Altera. I also note that the release notes for the latest Quartus mention that timing models have been changed for the Arria V series. 

 

I'll report back if something changes.
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