MAX 10 FPGA with ethernet to UART transparent bridge and NIOS V

[ericn]

Hi All,

 I have an application where I want to use the 10/100/1000 ethernet IP and then convert that to two UARTs inside the MAX 10 FPGA. I want to do what the WCH CH9121 device does: an ethernet to serial transparent bridge device but with up to gigabit ethernet support. Can someone give me some pointers on how to do this? My expertise is not in ethernet connectivity "yet" and I need some guidance on how to do this. 

I would also like to use the NIOS V processor inside the MAX 10 device. How fast can the Nios V go if I target the 10M08SAE144C8G device? Can I get away with using the 10M02 device? 

Also, can I do a block diagram/schematic for the top module and create the processor module, ethernet IP, and other components in the block diagram/schematic? I am a visual person and like to see the connections and also gives me more flexibility if I need to add some other functions later. Basically building it up as I go.  Any help is greatly appreciated :-).

Thanks,

Eric Norton

[ZiYing_Intel]

Hi Eric,

Are you want the design which have the IP setting as below requirements:

1. MAC
2. Gigabit

Besides that, can you do a block diagram for top module so that I can have a better understanding about your design?

To get more information about the ethernet IP, you may refer to the link below https://www.rocketboards.org/foswiki/Main/WebHome

Besides that, you can visit our FPGA design store webpage which got a lot example design that you can refer to https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html

Best regards,

zying

[ericn]

Hi Zying,

 I would like to have a self-contained 10/100/1000 ethernet controller with MAC and also be able to send and receive UART data all on its own without CPU intervention. I want to mimic what the CH9121 device does but place all of this logic inside the FPGA and then be able to communicate to the NIOS V processor through RX/TX lines of this "ethernet controller". I am not that familiar with the inner workings of ethernet communication yet so I have a bit to learn but looking for some guidance on how to implement something like this. I may be able to draw a block diagram of how I think it might work but may take a couple of days. I'm getting back into the FPGA design again and I am a bit rusty with all of this. Any help is greatly appreciated.

Thanks,

Eric Norton

[ZiYing_Intel]

Hi Eric,

Unfortunately we don't have the example design that you described in the thread.

For further information about the 10/100/1000 ethernet IP, you may refer to link below https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/about-this-ip.html

For further information about the NiosV processor, you may refer to link below https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/v.html

Best regards,

zying

[ZiYing_Intel]

Hi Eric,

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Best regards,

zying