PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING logic option

[Altera_Forum]

Hi, 

 I observe that in the 15.0 quartus setting file reference manual that there is a PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING logic option which is claimed to be appropriate for all device families.   I have attempted to use this option in several ways for Stratix IV as follows without obtaining my desired result.  Approach 1: set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING OFF -to <PLL name> -entity <entity name>  Approach 2: set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING OFF -to <PLL tap name> -entity <entity name>  My application is clocking DDR input channels from ADCs with two lanes of data for each ADC channel. My design employs independent ADC input clocks, one for each ADC channel. Each of these clocks is implemented as a separate and independent per-channel PLL tap.  My desired outcome from quartus and timequest would be for quartus to adjust the phases of each PLL tap individually to ballpark center setup and hold timing. Later when the system comes up software will calibrate the phase of each PLL tap individually to optimize margins.  Does anyone have experience with logic option PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING? Alternatively, perhaps someone will have suggestions on how to constrain IO interfaces that are dynamically PLL clock phase calibrated with software. Hopefully quartus can be configured to at least minimize the capture skew of the two bits per channel with respect to each other. I have looked briefly at how the uniphy timing scripts are implemented, but this approach appears to involve a fair amount of effort along with complexity. Hopefully there is a simpler way to constrain dynamically calibrated interfaces?  Thanks

[Altera_Forum]

Hi, 

 To allow the fitter to set the phase shift of a PLL output counter, you can try as below: set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to <to> -entity <entity name> <value>