Presettable and clearable registers converted to equivalent circuits with latches....

Altera_Forum · ‎07-06-2013

"warning (13004): presettable and clearable registers converted to equivalent circuits with latches. registers power-up to an undefined state, and devclrn places the registers in an undefined state."

Basically, what I did is that using "assign" statement to do some arithmetic calculations based on the current states of the registers. Then, at the next posedge of clock, update the same group of registers using these computational results. Therefore, there are some feedback loops controlled by the clock.

I have carefully checked all the used registers have initial states via a reset signal. Initialization via "initial" block didn't help.

Altera_Forum · ‎07-07-2013

I mean to remember that the nature of the problem is explained in detail in the device manuals.

The equivalent circuit with latches will be required for all recent FPGAs that don't have both asynchronous set and clear for registers, respectively an asynchronous load.

Consider the below register descriptions. Both can be only synthesized as an "equivalent circuit".

always @(posedge aload or posedge clock)
  if (aload)
    q <= s;
  else
    q <= d;

always @(posedge reset or posedge set or posedge clock)
  if (reset)
    q <= 1'b0;
  else if (set)
    q <= 1'b1;
  else
    q <= d;

The equivalent circuit is shown in a previous thread. http://www.alteraforum.com/forum/showthread.php?t=36490