JTAG Secure mode
I'm looking for more information regarding the JTAG Secure mode. It's mentioned a little in the MAX10 Configuration Guide: https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_config.pdf But I still don't get a full picture. I wonder if the JTAG is "LOCKED" by user logic or is there some kind of permanent switch that forces the device to go into that mode right after power on. If it's done by user logic, does it mean that, if I hold nCONFIG low, I will be able to erase the internal flash and get out of that "JTAG secure" mode? I appreciate your sharing of knowledge.
Hi Nhu-Ha Yup,
There is no switch to change your device in JTAG Secure Mode. You will need to enable the mode in Quartus, compile and generate a POF bitstream.
Enabling JTAG Secure Mode will cause your device to be able to use the instruction as shown at table below:
Thank you for answering my question, Please let me clarify,
It is easy to create the POF with JTAG -enable in Quartus tool (using convert file) of the document above.
1) Page 55. after power up and configuration of the JTAG-ENable. POF, MAX 10 is in JTAG secure mode.
page 56 To disable if "trigger the start_unlock port of the user logic) and issue UNLOCK JTAG INSTRUCTION.
The device exits from JTAG secure mode.
Do I need to pull nConfig pin LOW ? (page 28 describes configuration sequence) . or do anything with nStatus, CONF_DONE?
After I enabled the JTAG secure mode, power off and on. I can't erase, configure or program the MAX 10 any more.
I pull on the UNLOCK I/O pin HIGH, it does not work. I send in UNLOCK instruction via
quartus_jli -c 2 unlock_208.jam -a unlock
Info: Running Quartus Prime Jam Tools
Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
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Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
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Info: refer to the applicable agreement for further details.
Info: Processing started: Mon Sep 23 16:36:14 2019
Info: Command: quartus_jli -c 2 unlock_208.jam -a unlock
Info: Using INI file /opt/intelFPGA/18.0/quartus/linux64/quartus.ini
Exit code = 0... Success
Info: Quartus Prime Jam Tools was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 194 megabytes
Info: Processing ended: Mon Sep 23 16:36:17 2019
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:0
'Purpose: To unlock
ACTION unlock = DO_UNLOCK;
IRSCAN 10, $041;
WAIT 100 USEC;
Please find my response below:
1) You dont need to pull the nCONFIG LOW, the configuration pin will pull itself. You will just need to issue UNLOCK JTAG INSTRUCTION.
2) May i know if it works after you issue UNLOCK JTAG INSTRUCTION?
This is weird. By right it should be able to program after you UNLOCK it. May i know, have you observed if "indicator" port is going HIGH? You may also refer to the steps to UNLOCK as shown at link below: