counter using seven segment display

Altera_Forum · ‎07-08-2013

I am trying to write a code in Verilog which should display from 00 to FF on seven segment. i have two segment display on my fpga board.

It will be great if somebody can help me with code. For convenience i am posting my code.

Do let me know where I am making the mistake. Hope to hear soon. If somebody can modify the code and correct it here, it would be of great help.

Please help me guys, I really need your help.

module hex2led( HEX, LED );

input [3:0] HEX;

output [6:0] LED;

reg [6:0] LED;

always @(HEX) begin

case (HEX)

4'b0001 : LED = 7'b1111001; //1

4'b0010 : LED = 7'b0100100; //2

4'b0011 : LED = 7'b0110000; //3

4'b0100 : LED = 7'b0011001; //4

4'b0101 : LED = 7'b0010010; //5

4'b0110 : LED = 7'b0000010; //6

4'b0111 : LED = 7'b1111000; //7

4'b1000 : LED = 7'b0000000; //8

4'b1001 : LED = 7'b0010000; //9

4'b1010 : LED = 7'b0001000; //A

4'b1011 : LED = 7'b0000011; //b

4'b1100 : LED = 7'b1000110; //C

4'b1101 : LED = 7'b0100001; //d

4'b1110 : LED = 7'b0000110; //E

4'b1111 : LED = 7'b0001110; //F

default : LED = 7'b1000000; //0

endcase

end

endmodule

Altera_Forum · ‎07-09-2013

Hi, you wrote too many thread in the forum for your (quite simple) project: http://www.alteraforum.com/forum/showthread.php?t=41385&p=171060#post171060 , http://www.alteraforum.com/forum/showthread.php?t=41213&p=170439#post170439 ....

Here you show only a partial design, that may not get mistakes (I don't know Verilog). We can't see problem from here.

Are you assigned the pins correctly ?

Is the counter counting ? at a correct frequency ? Does it stop when it has reached the max or does it looping ?

Do you simulate your design ? (a little work)

Did you have error/warnings from Quartus compilation ?

Have you succeeded in configuring FPGA ? Maybe you compile for wrong FPGA.

Have you succeeded in configuring FPGA with simpler project : trun on a LED with a button ?

please put, in only one thread, your entire project that you have zipped before : see Quartus project menu > archive project OR compress your project directory, if it is not too big, and attach it in one thread.

Altera_Forum · ‎07-10-2013

--- Quote Start ---

Hi, you wrote too many thread in the forum for your (quite simple) project: http://www.alteraforum.com/forum/showthread.php?t=41385&p=171060#post171060 , http://www.alteraforum.com/forum/showthread.php?t=41213&p=170439#post170439 ....

Here you show only a partial design, that may not get mistakes (I don't know Verilog). We can't see problem from here.

Are you assigned the pins correctly ?

Is the counter counting ? at a correct frequency ? Does it stop when it has reached the max or does it looping ?

Do you simulate your design ? (a little work)

Did you have error/warnings from Quartus compilation ?

Have you succeeded in configuring FPGA ? Maybe you compile for wrong FPGA.

Have you succeeded in configuring FPGA with simpler project : trun on a LED with a button ?

please put, in only one thread, your entire project that you have zipped before : see Quartus project menu > archive project OR compress your project directory, if it is not too big, and attach it in one thread.

--- Quote End ---

I am just too tense that's why i did that..can you send me a code snippet in verilog of my problem.

I will be thankful to you.

Regards

Muz

Altera_Forum · ‎07-10-2013

You haven't got any error when Quartus compiles ?

Could you post here a compressed file (zip, 7z...) containing all your project sources ?

Because I don't know Verilog, hope somebody else will help you (if it is a Verilog problem but I doubt)

It may be a clock problem, reset problem, counter that doesn't loop, that count very too fast... So with partial sources you posted, hard to help you.

go fishing to cool down the brain ;-)