error: cannot synthesize non-constant real objects or values

[Altera_Forum]

Hi, 

 I used the code below to create a block that generates a random signal at the output with quartus ii: ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.math_real.ALL; -- for UNIFORM, TRUNC functions USE ieee.numeric_std.ALL; -- for TO_UNSIGNED function ENTITY tri_state_buffer_1 IS PORT ( --oe_input_name : IN STD_LOGIC; --data_input_name : IN STD_LOGIC; sNoise : buffer STD_LOGIC ); END tri_state_buffer_1; ARCHITECTURE arch_tri_state_buffer_1 OF tri_state_buffer_1 IS BEGIN  PROCESS  VARIABLE seed1, seed2: positive; -- Seed values for random generator  VARIABLE rand1 : real; -- Random real-number value in range 0 to 1.0  VARIABLE seed3, seed4: positive; -- Seed values for random generator  VARIABLE rand2 : real; -- Random real-number value in range 0 to 1.0  VARIABLE width: time; -- noise pulse width  VARIABLE interval: time; -- noise interval  BEGIN  seed1 := 7;  seed2 := 1;  seed3 := 8;  seed4 := 5;  LOOP  UNIFORM(seed1, seed2, rand1);  UNIFORM(seed3, seed4, rand2);  width := (rand1*0.00000001)*1 sec;  interval := (rand2*0.0000001)*1 sec;    Wait FOR width;  sNoise <= NOT(sNoise);  Wait FOR interval;  sNoise <= NOT(sNoise);  END LOOP;    END PROCESS; END arch_tri_state_buffer_1;  ---------------------------------------------------------------------------- When I click "create symbol" there is no error and warning. But, when I use it in schematic and compile, I receive below errors:  Error (10414): VHDL Unsupported Feature error at tri_state_buffer_1.vhd(17): cannot synthesize non-constant real objects or values Error (10442): VHDL Process Statement error at tri_state_buffer_1.vhd(16): Process Statement must contain either a sensitivity list or a Wait Statement Error (12152): Can't elaborate user hierarchy "tri_state_buffer_1:inst" !

[Altera_Forum]

the errors are quite clear - the real type is for simulation only when not used for a constant. 

Also, wait statements are not synthesisable.  For schematics, you can only create synthesisable code.  For a synthesisable random construct - google Linear Feedback Shift Register.

[Altera_Forum]

thanks for your helpful reply ;)

[Altera_Forum]

hi, 

what is the reason for real type to use in simulation and not to be able to synthese it. thank you

[Altera_Forum]

The real type has no bitwise representation, hence why it cannot be synthesised.

[Altera_Forum]

So what is the purpose of it at all?  

Why to simulate something that is not synthesised ?  Let me check that i understood correct, there is no float in VHDL? Is there any way to : count <= count + 0.0001;

[Altera_Forum]

--- Quote Start ---  So what is the purpose of it at all?  Why to simulate something that is not synthesised ?  Let me check that i understood correct, there is no float in VHDL? Is there any way to : count <= count + 0.0001;  --- Quote End ---    Because you may want to use real values as part of some model, or to calculate constant values, or generate random numbers in your testbench.  If count is declared as real, then your statement is perfectly valid VHDL - you just cannot synthesise it for an FPGA. If you want to do floating point synthesised code, you'll need to use the floating point IP cores that are available in the IP catalog in quartus. The signals used here will be std_logic_vectors. Or if you want to be adventurous, you could use the float_pkg available in VHDL 2008.

[Altera_Forum]

ok, thank you. 

I will try.