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I have issue with "Arm DS 2020.0 Intel Edition Toolkit" , i am running my ARM
DS2020 debugger on windowd 10 (64 bit machine)
Earlier i am using ARM DS-5 along with Quartus16.1 and i am running
ARRADIO
( see the web link) application without any issue on Cyclone V SoC Kit,
I have connect AD9361 board to by SoC Kit through HSMC
i have download from GitHub:
(Master)https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw
now recently i have purchase Arm DS Intel Edition Toolkit (2020), and
also quartus 20.1 but nothing is working here, some how i am able to
compile RTL Project on quartus, but every time i run my ARRADIO Software
on ARM DS2020 it generate below error.I have compile the project on
Quartus16.1 & Quartus 18.1 also but no gain.
Error is :
Stopping running target Intel SoC FPGA - Cyclone V SoC (Dual
Core) on connectionConnected to running target Intel SoC FPGA - Cyclone
V SoC (Dual Core)Execution stopped in SVC mode at
S:0x00000964S:0x00000964 TST r1,#1cd
"D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361"Working
directory
"D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361"Execution
stopped in SVC mode at S:0x00000964S:0x00000964 TST r1,#1source /v
"C:\Program Files\Arm\Development Studio
2020.0\sw\debugger\configdb\Scripts\altera_target_check.py"+print
&$Peripherals::$rstmgr::$rstmgr_brgmodrst$1 = (unsigned int*)
P:0xFFD0501CCannot access FPGA to check SYS ID registers, expected
values are:Expected value of
Peripherals::altera_avalon_sysid_c5soc_sys_id_control_slave::altera_avalon_sysid_c5soc_sys_id_control_slave_ID:0xacd51302/0xffffffffExpected
value of
Peripherals::altera_avalon_sysid_c5soc_sys_id_control_slave::altera_avalon_sysid_c5soc_sys_id_control_slave_TIMESTAMP:0x5f7e9174/0xfffffffffile
"D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361\u-boot-spl"set
debug-from mainstartStarting target with image
D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361\u-boot-splRunning
from entry pointWARNING(CMD399-COR168):! Failed to start the target! No
function named "main" could be foundWARNING(CMD407): Trying the entry
point insteadwaitExecution stopped in SVC mode at S:0xFFFF0000In
start.SS:0xFFFF0000 39,0 _start: b resetsource /v
"D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361\debug-hosted.ds"+reset
systemERROR(CMD463):# in
D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361\debug-hosted.ds:8
while executing: reset system! The reset capability system is not
availableERROR(CMD656): The script
D:\Q16.1User\2016_R2\Software\ad9361_demo_application\ad9361\debug-hosted.ds
failed to complete due to an error during execution of the script
Any help/suggestion in this regard is highly appreciate .
Regardskaushal
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Currently i am working on Quartus18.1
Adding peripheral description file from directory
D:\Q18.1User\2018_R2_Master\hdl-master\hdl-master\projects\arradio\c5soc\system_bd\synthesis
further gives error like not able to understand "./sw/ad9361.o" file
16:31:19 **** Incremental Build of configuration Debug for project ad9361 ****
make all
Building target: ad9361.axf
Invoking: Arm Linker 6
armlink.exe --cpu=cortex-a9 --scatter="D:\Q18.1User\2018_R2_Master\hdl-master\hdl-master\projects\arradio\c5soc\software\ad9361\sw\scatter.scat" --info=sizes -o "ad9361.axf" ./sw/ad9361.o ./sw/ad9361_api.o ./sw/ad9361_conv.o ./sw/adc_core.o ./sw/command.o ./sw/console.o ./sw/dac_core.o ./sw/main.o ./sw/platform.o ./sw/util.o
Fatal error: L6007U: Could not recognize the format of file ./sw/ad9361.o.
Finished: 0 information, 0 warning, 0 error and 1 fatal error messages.
make: *** [makefile:47: ad9361.axf] Error 1
"make all" terminated with exit code 2. Build might be incomplete.
16:31:19 Build Failed. 2 errors, 0 warnings. (took 406ms)
plz suggest how to resolve this issue ?
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Hi ,
Please let us know whether you are trying to use the PRO version of Standard version of Quartus , Also please share the error logs which are obtained while using Quartus 20.1 and DS2020.
Also if possible enable the internal error log and provide us the details .
Thanks and Regards
Anil

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