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QFSP design example for Stratix 10


I found a design example using QFSP for my design. I received it from S10-SoC_H-Tile_DevKit_v1.0  would like to leverage  this design as much as possible. 

Since I want to use QFSP in this design I have removed fsp components to begin with.

The design is using JTAG to AvMM to connect to QFSP (I think) from Host.

1) As such I would like to additionally place a  dma, probably of mSGMDA type so to move  data out of the sodimm to qfsp. It seems I need to keep JTAG Avm in the design.

I will use a heretical mode so keep my SODIMM and QFSP in their original form as much as possible.

2) I need to disable the pattern generation and all component of loop back which are used/enabled in this design? (not sure to disable or leave it as it is?). They are located in the test module. 

3) I need to take the parallel data from DMA (from SODIMM) to QFSP. Should I use streaming method of Avalon buss? Where should I connect them to in the QFSP module? directly to xcvr_test_system by exporting fifo input? or other blocks in side.

I can't find any recipe/document to show what each module does or what to do?

Also in most of your intel documentation it seems the main focus is to talk about the capability of this great tool and lots of verbiage but little as how of step by step process. Could you please provide this feedback to your development team.


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1 Reply

Hi ,

Thanks for providing an honest feedback.

Please use our existing design examples as a starting point for customizing the design.

If you need exact step by step procedure on customizing the design please contact the local sales team so that

we can try to arrange a dedicated support for you based on the business value proposition.

Thanks and Regards


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