PIO INTERRUPT

Altera_Forum · ‎09-07-2004

i configed the pio_1 of my nios II as synchronously capture,either edge,interrupt generated by edge.

before i call the isr,i enable the irq of pio_1 by write the code as bellow:

void* edge_capture_ptr = (void*) &edge_capture;

/* Enable all 4 button interrupts. */

IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_1_BASE, 0xf);

/* Reset the edge capture register. */

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_1_BASE, 0x0);

/* Register the interrupt handler. */

alt_irq_register(PIO_1_IRQ, edge_capture_ptr,pio_interrupt_handle );

//it is almost as same as provided in the sample program(count binary);

then i connected pio_1 to the internal logic singal in the same FPGA,and expecte to read the PIO_1 edge_cap the another pio_0;but I did not found the isr run.

and I found a function alt_irq_enable-all();but this function is only used when nested irq are runing.

my question is:

must I connect the pio to signals from out of the FPGA(I think it need not to do so);

must I enable all the irq?but there is no global irq enable register in nios II,and I find there is no

such code in the example count binary.c http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ph34r.gif

Altera_Forum · ‎09-07-2004

hi all

I do capture the edge ,so it seems that we can connect the interrupt singal from inside the fpga.

then why i find that the code inside isr (pio_interrupt handle) was not executed?

the first argument in alt_irq_register() is PIO_1_IRQ,and the third argument is the isr (pio_interrupt handle);

I can find any mistake in my code.

BTW,my nios II only has tow periphery.:pio_0 and pio_1;

and the on chip memory is 8kx32bits.

does the nios II isr need large memory space? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

Altera_Forum · ‎09-23-2004

I didn't see a line of code that sets the PIO pins to inputs. I think that is necessary to use them for interrupts.