Does anyone have instructions for building the fpga image for the nios example for the cyclone 3 starter board.I can build the 'my first fpga' image (not tried to download it). qsys has converted the sopc file, but I can't generate the fpga image - I think loads of files are missing, starting with sys_pll.v. The altera doc assumes you are going to run a pre-built image. I was hoping to use it to write/test some custom instructions. Using a small dev board will give much faster complatioon times that using one of our own boards. FWIW I'm hoping to run on linux (rather than windows), the tools (13.1.1) seem to be running fine - apart from the qsys window not being movable from the top left corner!
The main project is missing all the qsys generated files....It looks like all the [file join $::quartus(qip_path) "foobar"] are failing as if qip_path has never been set. Perhaps a problem with the conversion of the project from 'sopc' to 'qsys', maybe an issue with case sensitive filenames (some strings have "SOPC" others "sopc"). I'm not sure what would set qip_path, the only references I can see are in 'file join' requests.
Solved by getting one of our HW guys to convert the project to 13.0 on a windows system and then copy the files over.I've also managed to move the qsys window from (0,0) - the 'workspace switcher' will let you move the window even though its title bar is hidden being the ubuntu window managers global title bar. I guess that the window is being explicitly placed at (0,0) instead of letting the window manager choose the location.