Costas Loop oscillates in ModelSim while locks in MATLAB!

[Altera_Forum]

Hello again, 

I have designed a Costas Loop in MATLAB and it simulates very well... locking and recovering the carrier. Here are the results:  http://www.alteraforum.com/forum/attachment.php?attachmentid=10456&stc=1   I ported the design to FPGA in VHDL, and simulated in ModelSim... however, the loop has a kinda oscillating behaviour... take a look:  http://www.alteraforum.com/forum/attachment.php?attachmentid=10457&stc=1   This is the Loop Filter output:  http://www.alteraforum.com/forum/attachment.php?attachmentid=10458&stc=1   Why is it oscillating? Is it the loop filter?

[Altera_Forum]

if your single clean tone is not having zero error then there should be something to explain. Either phase of Tx tone is not same at the Rx nco or your branch filters are doing something not very nice such as not cutting off well or cutting off your own wanted signal. You can check spectrum at each stage using sptool or any fft based approach. 

 if your external nco has phase control input that controls phase only and doesn't change its running frequency (apart from transient effect of phase change) then you complete the loop in the same way using the filtered error and scale it to match the phase register range but without the need to revert back to control frequency.   In any case the error should be scaled correctly. The principle of the Costas phase error (real * imag) is that error = -1/4*sin(2*phase diff). in this design we are not looking at phase diff directly but its -sine which goes down then up then down depending as angle diff goes up... in other words the error could change sense if it overshoots by 1/4 cycle. The alternative is to get phase diff itself instead of sin(e.g. using cordic) plus phase unwrapping. This way you make sure the error sense is fixed either up or down. This could make control easier?  notice also that sin function for 1/4 cycle is nonlinear and horribly so at 90 degree section, only the first half of it i.e 45 degrees is linear enough.  so in short, keep using the error as it is (sin) and modify further if necessary. Good luck.

[Altera_Forum]

Thank you very much Mr Kazem I'm really grateful for your assistance and support. It's an honour to meet someone like you. Zor Spass :D 

By the way.. can I have your email or linkedin profile? if you don't mind of course.

[Altera_Forum]

One thing to be aware that we might have got lost in. Your input must be BPSK i.e. one stream (not I/Q as my qpsk example) I hope you were not using qpsk. 

 will send you my email. My profile here got my complete name (I think) and just type it for linkedin.

[Altera_Forum]

looks like emails are disabled 

kadhiem_ayob@yahoo.co.uk

[Altera_Forum]

I hope I was using QPSK... at least I could have another hope :) But I've just made my decision... I'm gonna use RTL-SDR Dongle... initial reading shows the chips has internal I/Q demodulator thus must lock by itself for a given frequency. Anyway I'll check it. 

 Actually I have found your profile on LinkedIn but I couldn't add you because they won't your email :D