Nios® V/II Embedded Design Suite (EDS)
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Question about shadow register

Honored Contributor II

Dear all, 

As describe in NIOSii reference book, when nios answer interrupt, the register is automatically switch to shadow ones configure with EIC.  

When NIOS executing ISR, the status of NIOSii is 0x418(shadow register 1, IL 1 and IH is set ), quiting ISR with eret (estatus 0x0), the status is  

set to 0, but sp is not changing back to the settings of original register, and actually I think NIOS SBT seems stopping update all the register value. 

I wonder if anyone know why NIOS SBT stop updating register value when 

returning from isr, or am I eret in the wrong way that the CPU failed to change back to origin register. 

Thanks very much!
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Honored Contributor II



I know its been a long time but were you able to figure out what was causing this issue? I've run into a similar problem and would appreciate you sharing your experience. 


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