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The more i work with nios the more funny task have to be solved :-)
As mentioned in a previous topic, i had designed an 8 bit avalon master. But we had to change the design to 32bit due to performance reason under worst case situation (not enough cycles left for all avalon masters to access sdram). Our SOPC has 3 Interfaces. ACS : Avalon Control Slave It has the registers for setup of our ip design. It also has the registers where the other 2 avalon masters get their start addresses from. ARM : Avalon Read Master it only reads from the memory and transfers data to acs. AWM : Avalon Write Master it writes data from acs to the memory The sopc component editor nios 5.1 wants that each Interface has its own clk source. Therefore our sopc module has 3 clk signals. acs_clk arm_clk and awm_clk. without them and just only 1 clk input we cannot finish the component editor. Using our module inside sopc where we have only 1 clk source for everything each interface is connected to the same clk as defined. But Quartus comlains that signals from one interface to another crosses a clock domain and therefore needs to be synchronised with 2 DFF. But things get more worse when we use the signaltap. Now we have hundreds of signals that are not correctly synchronised and on some boards we cannot program the cfi flash with such a design. has anybody any recommendation what we should check ? implementing 2 DFF for each bit that goes f.e. from acs to arm will lead to a big amount of addition registers. i would agree if we had more than one clk source, like fast_clk for nios and slow_clk for our ip, but the whole design uses the same clock source. Any comment greatly welcome. Michael SchmittLink Copied
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Hello Michael,
I think you only need one clock in the Component Editor if you select the interface “global_signals” in the Signals Tab. Regards, niosIIuser- Mark as New
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hmmmm that could be a solution and is currently in Analysis and Synthese Flow ....
Michael Schmitt
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