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SOPC components and successful connection to NIOS II

Altera_Forum
Honored Contributor II
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Is it necessary for all SOPC components to be working correctly to establish a successful connection with the NIOS Processor. 

 

Say I am writing a custom avalon-mm PWM module and it is still in its debug stages and I include it in a previously working SOPC System with NIOS. 

 

Is it possible to establish a connection with the NIOS via downloading an elf to it even while that PWM module is incomplete but compiles successfully. 

 

In reality, the module I am adding and customizing is a DDR controller. I can't seem to Download a helloworld elf file or even establish a connection to the NIOS using system-console.
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Altera_Forum
Honored Contributor II
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Hi, 

 

It's quite easy for your half finished Avalon master to hang the bus and thus prevent the CPU from accessing memory. Is there some other way you can arrange your bus connections to isolate it? Or even leave it out for now by checking the box next to it in SOPC builder and leaving it disabled until its more finished. 

 

Mark.
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Altera_Forum
Honored Contributor II
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There is that way, but the main reason for not disabling the module is so that I can debug it using NIOS II since I thought it would be the easiest way to debug the custom memory controller in a way that I can use STDIO to read and write to the memory or simply have a C routine to write and read it back and at the same time, I can probe the control signals that the controller uses.

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Altera_Forum
Honored Contributor II
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You might want to have a look at System Console. You could do the same thing Nios II does in TCL. I would start with having just your component, a simple onchip RAM and a JTAG to Avalon-MM bridge component. It will be apparent if/when you deadlock your system and I believe there's even a PLI mode where you could simulate before even trying it in-FPGA. 

 

Cheers, 

 

slacker
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Altera_Forum
Honored Contributor II
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That's normally what I do first. I go to NIOS system console do the following 

 

set sysid $3010 

set mm [ lindex [ get_service_paths master ] 0 ] 

processor_stop $mm 

open_service master $mm 

master_read_32 $mm sysid 2 

(that returns the sysid and the timestamp) 

close_service master $mm 

 

This works 100% all the time returning the sysid and the timestamp without the custom DDR Controller. But as soon as I enable use of the DDR controller, the console hangs at the command 

processor_stop $mm 

and gives the error Target is Broken and needs to be reset. Also, I am using onchip ram for my processor instruction, data, reset and exception vectors. I have attached the following images as added information: 

 

SOPC Build 

http://www.flickr.com/photos/62267943@n04/5665878428/in/photostream/ 

 

SystemConsole Error 

http://www.flickr.com/photos/62267943@n04/5665310823/in/photostream/ 

 

BSP Editor Linker 

http://www.flickr.com/photos/62267943@n04/5665878672/in/photostream/
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Altera_Forum
Honored Contributor II
315 Views

Ok. You don't have to have a processor when initially testing the memory. As I mentioned, I would use the JTAG to Avalon MM Bridge/Master instead. 

 

Also, you definitely want to make sure that odd things aren't happening with key signals on the Avalon-MM side of things in your component...particularly waitrequest. 

 

Regards, 

 

slacker
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Altera_Forum
Honored Contributor II
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If I were you, I would also place a SignalTapII on you custom interface and on the state machine that manages it to understand what hangs everything. But probably you have already tried.

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Altera_Forum
Honored Contributor II
315 Views

 

--- Quote Start ---  

That's normally what I do first. I go to NIOS system console do the following 

 

... 

 

This works 100% all the time returning the sysid and the timestamp without the custom DDR Controller. But as soon as I enable use of the DDR controller, the console hangs at the command 

processor_stop $mm 

and gives the error Target is Broken and needs to be reset. Also, I am using onchip ram for my processor instruction, data, reset and exception vectors. I have attached the following images as added information: 

 

--- Quote End ---  

 

 

If the processor_stop command hangs then this probably means that the processor is unable to go into debug mode. The most likely reason for this is that the processor is unable to complete the current instruction, for example because the code at the reset address was trying to read from the DDR controller. 

 

You might want to try using processor_reset instead of processor_stop - that will reset the processor before putting it into debug mode, a solution which should work.
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Altera_Forum
Honored Contributor II
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Bump. Anyone determine the root cause for this processor hanging? Using processor_reset didn't seem to help.

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