Nios® V/II Embedded Design Suite (EDS)
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Simulating Software Running on a Nios II Processor

Honored Contributor II

Hi, I got problem when Simulating Software Running on a Nios II Processor. The Nios II Processor is generated by Qsys. The step is as follow: 


1. On the Generation tab, set Create testbench Qsys system to Simple, BFMs for clocks and resets. 

2. Set Create testbench simulation model to Verilog. 

3. Click Generate. 

in qsys, i create the system with nios ii processor、onchip_ram、jtag_uart and pio. 


1. Open the Nios II SBT for Eclipse. 

2. Set up an application project and board support package (BSP) for the 

<qsys_system>.sopcinfo file. 

3. To optimize the BSP for simulation and disable hardware programming, 

right-click on the BSP project and choose Properties, then choose Nios II BSP Properties, and turn on ModelSim only, no hardware support. 

4. To simulate, right-click on the application project in Eclipse, point to Run as and choose 4Nios II ModelSim. The Run As Nios II ModelSim command sets up the ModelSim simulation environment, compiles and loads the Nios II software simulation. 

5. To run the simulation in ModelSim, type run -all in the ModelSim transcript window. 

in sbt, i only do the i/o operation about "iowr(pio_0_base,0,0x12345678)" 

The problem is that I can't see the waveform of "IOWR" opertation to pio, the write signal of pio is always invalid. How can I see the right waveform? 

Thank you!
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Honored Contributor II

I also could not get a simple hardware up. There seems to be something strange in the "memory initialisation file" file setting for the onchip ram. 


IF the memory name is InsMem then two .hex files are created. One in the Qsys folder (InsMem.hex) and another in the "synthesis" folder (InsMem_mem.hex) The InsMem.v seems to access the InsMem.hex and the .qip file (added to quartus) the "InsMem_mem.hex" 

The NIOS IDE only accepts the InsMem.hex. Do'nt know what file the Quartus uses to update MIF, but both seem to be called. 


I update the MIF file and configure the FPGA using an intelligent host. External logic is fine, but NIOS work run. Looks like memory is not getting updated. 

Same technique worked fine in Quartus 10/SOPC with no problem.
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