Nios® V/II Embedded Design Suite (EDS)
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accelerate cyclone V

Honored Contributor II

Hi All, 


I am using cyclone V SOC kit from Terasic. 


Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to funcation with low latency. I made hps to fpga bridge connection for Light weight hps to FPGA communication. 


Now I want to improve throughput and letency of communication between HPS and FPGA. any one can please suggest me to do so?? 


P.S : I go through exaple of Datamover; so I have another question that Is it necessary to use NIOSII Qsys componebt; if yes then could anyone explain How Nios II help to improve communication between h2f and f2h? 


Thanks in advance.
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