Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Altera Modelsim

Altera_Forum
Honored Contributor II
‎09-07-2011 06:36 AM
1,373 Views

I have a very simple design in Quartus Web Pack ver 11.0 , and with it i have Modelsim-Altera Starter ver 6.6d. I get these error messages "vsim-19" when i do rtl-level simulation . 

 

"failed to access library tb_xxx st tb_xxx" 

 

 

I used the same vhdl files and run the simulation in Modelsim ver 6.2 SE and i see results as expected ??? 

 

I have checked the mapping of lib using vmap it is ok . 

 

What is the problem ??? 

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Altera_Forum
Honored Contributor II
‎09-07-2011 07:27 AM
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From your picture, there is no tb_ezusb library.

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Altera_Forum
Honored Contributor II
‎09-07-2011 09:15 AM
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This is how i have set up the test bench .

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Altera_Forum
Honored Contributor II
‎09-07-2011 05:21 PM
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i have a simple counter design with the same tb setup and its RTL simulation works.

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