Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20713 Discussions

Altera Modelsim

Altera_Forum
Honored Contributor II
‎09-07-2011 06:36 AM
1,087 Views

I have a very simple design in Quartus Web Pack ver 11.0 , and with it i have Modelsim-Altera Starter ver 6.6d. I get these error messages "vsim-19" when i do rtl-level simulation . 

 

"failed to access library tb_xxx st tb_xxx" 

 

 

I used the same vhdl files and run the simulation in Modelsim ver 6.2 SE and i see results as expected ??? 

 

I have checked the mapping of lib using vmap it is ok . 

 

What is the problem ??? 

</SPAN>
Preview file
166 KB
0 Kudos

Link Copied

3 Replies
Altera_Forum
Honored Contributor II
‎09-07-2011 07:27 AM
365 Views

From your picture, there is no tb_ezusb library.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎09-07-2011 09:15 AM
365 Views

This is how i have set up the test bench .

Preview file
164 KB
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎09-07-2011 05:21 PM
365 Views

i have a simple counter design with the same tb setup and its RTL simulation works.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.